CS4373 Datasheet, PDF (5/20 Pages) Cirrus Logic – Low-power, High-performance Delta-Sigma Test DAC

CS4373
ANALOG CHARACTERISTICS (CONTINUED)
Parameter
Analog Outputs
Differential Output Level
Absolute Accuracy
Relative Accuracy
Offset Error
Full Scale Drift
Offset Drift
Analog Output Load at BUF±
Voltage Reference Input
VREF
VREF Current
Power Supplies
Power Supply Rejection
DC Power Supply Currents
Symbol Min
V_DIF
-
ABS
-
REL
-
VOS
-
(Note 3) FSD
-
(Note 3) VOD
-
Load Resistance
R_L
1
Load Capacitance
C_L
-
(Note 4, 5) VREF_V
-
VREF_I
-
(Note 6) PSRR
90
(Note 7 and 8)
Typ
-
±1
±0.2
-
5
1
-
-
2.5
-
-
Max Unit
5
±2
±1.8
1
-
-
-
100
V_P-P
%FS
%FS
%FS
ppm/°C
µV/°C
kΩ
pF
-
V
120
µA
-
dB
Normal Power Mode
LPWR = 0; MCLK = 2.048 MHz
Analog VA
Digital VD
-
7.8
-
mA
-
100
-
µA
Low Power Mode
LPWR = 1; MCLK = 1.024 MHz
Analog VA
Digital VD
-
5.0
-
mA
-
100
-
µA
Power Down Mode
Analog VA
Digital VD
-
400
-
µA
-
100
-
µA
Sleep Mode
Analog VA
-
2
-
µA
Digital VD
-
2
-
µA
3. Specification is for the parameter over the specified temperature range and is for the CS4373 only and
does not include the effects of external components.
4. A 2.5 V voltage reference results in the highest dynamic range and best signal-to-noise performance,
though smaller reference voltages may be used.
5. VREF is defined as {(VREF+) - (VREF-)} and Inputs must satisfy: VA- < VREF- < VREF+ < VA+
6. Power Supply Rejection is tested by applying a 100 mV_P-P 50 Hz signal to each supply.
7. All outputs unloaded. All digital inputs forced to VD or GND respectively. VA+ = 5 V; VA- = 0;
VD+ = 3.3 V.
8. In Low Power Mode LPWR = 1, the Master Clock MCLK is reduced to 1.024 MHz. This reduces the
signal bandwidth by a factor of 2.
DS577F1
5