CS4373 Datasheet, PDF (17/20 Pages) Cirrus Logic – Low-power, High-performance Delta-Sigma Test DAC

11.PIN DESCRIPTION
CS4373
Positive Capacitor Output CAP+ ₁
Negative Capacitor Output CAP- ₂
Positive Buffered Output BUF+ ₃
Negative Buffered Output BUF- ₄
Positive High Precision Output OUT+ ₅
Negative High Precision Output OUT- ₆
Positive Analog Power Supply
VA+ ₇
Negative Analog Power Supply
VA- 8
Negative Voltage Reference VREF- 9
Positive Voltage Reference VREF+ 10
No Connect
NC 11
No Connect
NC 12
No Connect
NC 13
No Connect
NC 14
28 ^{LPWR Low Power Mode Enable}
27 ^{MODE0 Mode Select}
26 ^{MODE1 Mode Select}
25 ^{MODE2 Mode Select}
24 ^ATT0
Attenuation Range Select
23 ^ATT1
Attenuation Range Select
22 ^ATT2
Attenuation Range Select
21 TDATA Signal Bitstream Input
20 VD
Positive Digital Power Supply
19 DGND Digital Ground
18 MCLK Master Clock Input
17 SYNC
Clock Sync Input
16 DNC
Do Not Connect
15 DNC
Do Not Connect
Pin Name Pin # I/O
Pin Description
CAP+, CAP- 1, 2 O External Capacitor Connection for Test DAC anti-alias filter
BUF+, BUF- 3, 4 O Buffered Output from the Test DAC
OUT+, OUT- 5, 6 O High precision output from the Test DAC
VA+, VA-
7, 8 I Power supply for the analog section. Refer to the Recommended Operating Conditions for appropri-
ate voltages.
VREF-,
VREF+
9, 10 I Voltage reference for the internal sampling circuits. Refer to the Recommended Operating Condi-
tions for appropriate voltages.
SYNC
17 I Clock Sync Input - A low to high transition resets the internal clock phasing of the DAC.
MCLK
18 I Master Clock Input - a CMOS compatible clock input for the DAC internal master clock.
DGND
19 I Digital Ground - Ground reference for the digital section.
VD
20 I Power supply for the digital section. Refer to the Recommended Operating Conditions for appropri-
ate voltages.
LPWR
28 I Low Power Mode Select - When set high the CS4373 enters into a Low Power Mode. (See Section
Section 9, "Power Modes" on page 15 for more on Power Modes)
TDATA
24 I Test DAC Signal Bitstream Input.
DS577F1
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