CS4373 Datasheet, PDF (14/20 Pages) Cirrus Logic – Low-power, High-performance Delta-Sigma Test DAC

CS4373
By placing known resistances on both BUF+
and BUF- (each side of the sensor) the voltage
at the buffered outputs (BUF+ and BUF-) can
be measured through the CS3301 or CS3302
and compared to the voltage on the precision
outputs (OUT+ and OUT-). From these mea-
surements the leakage current of the sensor
can be determined
Linearity can also be measured from the out-
put of OUT±. And when connected to the digi-
tal filter, a digital impulse bitstream can be fed
directly to the CS4373 to test the impulse re-
sponse of the system.
7.3 Test Mode 2: Electronics Test Mode
In this test mode, outputs BUF± are high-Z and
only OUT± is available. BUF± become high im-
pedance to protect any external sensors still
connected. This mode can be used to test oth-
er system electronics on the board. It should
be noted that since only OUT± can be used in
this mode, and OUT± are unbuffered outputs,
OUT± can only be connected to a high imped-
ance load, such as the CS3301 and CS3302
amplifiers.
7.4 Test Mode 3: Sensor Test Mode
As opposed to Test Mode 1, in this mode
BUF± are the only available outputs. This
mode offers another option to test external cir-
cuitry. While operating in Test Mode 3, OUT±
are high impedance to ensure no interference.
7.5 Test Mode 4: Common Mode
In this mode the system can be tested using a
common mode output from both BUF± and
OUT±. Figure 7 shows BUF± and OUT± con-
nections internal to the CS4373. Again, since
the OUT± pins are unbuffered, they must only
be connected to a high impedance load, such
as the CS3301 and CS3302.
7.6 Test Mode 5: High Voltage/High
Current Mode
This mode allows connection of the OUT± pins
to high voltage or high current electronics.
Figure 8 shows a typical connection diagram
for this operational mode. The CS3301 and
CS3302 amplifiers can be used in the configu-
ration as the precision buffers. When using the
circuit in Figure 8, the gain of the circuit is de-
fined as:
( ) ^A_V ⁼
V₂
V₁
=
1+ ^2R1
R₂
High Current/
High Voltage
V₂
Electronics
10nF
COG
CAP+
CAP-
CS4373
BUF+
+
-
R₁
R₂
R₁
-
+
BUF-
OUT+
V₁
OUT-
Figure 8. Test Mode 5
7.7 Test Mode 6: Reserved
7.8 Test Mode 7: Sleep Mode
In this mode the chip is put into a low power
sleep mode (See Section 9, "Power Modes"
on page 15 for more).
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DS577F1