CS42438_07 Datasheet, PDF (49/61 Pages) Cirrus Logic – 108 dB, 192 kHz 6-In, 8-Out TDM CODEC

7.12 ADC Channel Invert (Address 17h)
7
Reserved
6
Reserved
5
4
INV_AIN6 INV_AIN5
3
INV_AIN4
2
INV_AIN3
1
INV_AIN2
7.12.1 Invert Signal Polarity (INV_AINX)
Default = 0
0 - Disabled
1 - Enabled
Function:
When enabled, these bits will invert the signal polarity of their respective channels.
CS42438
0
INV_AIN1
7.13 Status (Address 19h) (Read Only)
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
CLK Error
2
1
ADC3_OVFL ^ADC2_OVFL
0
ADC1_OVFL
For all bits in this register, a “1” means the associated error condition has occurred at least once since the
register was last read. A”0” means the associated error condition has NOT occurred since the last reading
of the register. Reading the register resets all bits to 0. Status bits that are masked off in the associated
mask register will always be “0” in this register.
7.13.1 CLOCK ERROR (CLK ERROR)
Default = x
Function:
Indicates an invalid MCLK to FS ratio. This status flag is set to “Level Active Mode” and becomes active
during the error condition. See “System Clocking” on page 33 for valid clock ratios.
7.13.2 ADC Overflow (ADCX_OVFL)
Default = x
Function:
Indicates that there is an over-range condition anywhere in the CS42438 ADC signal path of each of the
associated ADC’s.
7.14 Status Mask (Address 1Ah)
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
CLK Error_M
2
ADC3_OV
FL_M
1
ADC2_OVFL_M
0
ADC1_OVFL_M
Default = 0000
Function:
The bits of this register serve as a mask for the error sources found in the register “Status (Address 19h)
(Read Only)” on page 49. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will
affect the status register. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not
affect status register. The bit positions align with the corresponding bits in the Status register.
DS646F2
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