CS42438_07 Datasheet, PDF(26/61 Page) Cirrus Logic – 108 dB, 192 kHz 6-In, 8-Out TDM CODEC

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CS42438_07 Datasheet, PDF (26/61 Pages) Cirrus Logic – 108 dB, 192 kHz 6-In, 8-Out TDM CODEC

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5. APPLICATIONS

CS42438

5.1 Overview

The CS42438 is a highly integrated mixed signal 24-bit audio CODEC comprised of 6 analog-to-digital con-

verters (ADC) implemented using multi-bit delta-sigma techniques and 8 digital-to-analog converters (DAC)

also implemented using multi-bit delta-sigma techniques.

Other functions integrated within the CODEC include independent digital volume controls for each DAC, dig-

ital de-emphasis filters for the DAC, digital volume control with gain on each ADC channel, ADC high-pass

filters, and an on-chip voltage reference,.

The serial audio interface ports allow up to 8 DAC channels and 8 ADC channels in a Time-Division Multi-

plexed (TDM) interface format. The CS42438 features an Auxiliary Port used to accommodate an additional

two channels of PCM data on the ADC_SDOUT data line in the TDM digital interface format. See âAUX Port

Digital Interface Formatsâ on page 34 for details.

The CS42438 operates in one of three oversampling modes based on the input sample rate. Mode selection

is determined automatically based on the MCLK frequency setting. Single-Speed Mode (SSM) supports in-

put sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-Speed Mode (DSM) supports

input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-Speed Mode (QSM) sup-

ports input sample rates up to 200 kHz and uses an oversampling ratio of 32x (Note: QSM for the ADC is

only supported in the IÂ²S, Left-Justified, Right-Justified interface formats. QSM is not supported for the

ADC). Note: QSM is only available in Software Mode (see âSystem Clockingâ on page 33 for details).

All functions can be configured through software via a serial control port operable in SPI Mode or in IÂ²C

Mode. A Hardware, Stand-Alone Mode is also available, allowing configuration of the CODEC on a more

limited basis. See Table 2 for the default configuration in Hardware Mode.

Figure 1 on page 11 and Figure 2 on page 12 show the recommended connections for the CS42438 in

Software and Hardware Mode, respectively. See âRegister Descriptionâ on page 41 for the default register

settings and options in Software Mode.

Function

Power Down ADC

Power Down DAC

Power Down Device

MCLK Frequency Select

Freeze Control

AUX Serial Port Interface Format

ADC1/ADC2 High Pass Filter Freeze

ADC3 High Pass Filter Freeze

DAC De-Emphasis

ADC1/ADC2 Single-Ended Mode

ADC3 Single-Ended Mode

AIN5 Multiplexer

Hardware Mode Feature Summary

Default Configuration

Hardware Control

All ADCâs are enabled

All DACâs are enabled

Device is powered up

Selectable between 256Fs and

512Fs

âMFREQâ pin 3

N/A

Left-Justified

High Pass Filter is always

enabled

High Pass Filter can be

enabled/disabled

âADC3_HPFâ pin 4

No De-Emphasis applied

Disabled

Selectable between Differential

âADC_SDOUT/

and Single-Ended

ADC3_SINGLEâ pin 13

Selects between AIN5A and

AIN5B when ADC3 in Single-

Ended Mode

âAIN5_MUXâ pin 1

Table 2. Hardware Configurable Settings

Note

see Section 5.4

see Section 5.2.5

see Section 5.2.2

DS646F2

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