CS42438_07 Datasheet, PDF (21/61 Pages) Cirrus Logic – 108 dB, 192 kHz 6-In, 8-Out TDM CODEC

SWITCHING SPECIFICATIONS - ADC/DAC PORT
(Inputs: Logic 0 = DGND, Logic 1 = VLS, ADC_SDOUT C_LOAD = 15 pF.)
Slave Mode
Parameters
Symbol
RST pin Low Pulse Width
(Note 17)
MCLK Frequency
MCLK Duty Cycle
(Note 18)
Input Sample Rate (FS pin)
Single-Speed Mode F_s
Double-Speed Mode (Note 19) F_s
Quad-Speed Mode (Note 20) F_s
SCLK Duty Cycle
SCLK High Time
t_sckh
SCLK Low Time
t_sckl
FS Rising Edge to SCLK Rising Edge
t_fss
SCLK Rising Edge to FS Falling Edge
t_fsh
DAC_SDIN Setup Time Before SCLK Rising Edge
t_ds
DAC_SDIN Hold Time After SCLK Rising Edge
t_dh
DAC_SDIN Hold Time After SCLK Rising Edge
t_dh1
ADC_SDOUT Hold Time After SCLK Rising Edge
t_dh2
ADC_SDOUT Valid Before SCLK Rising Edge
t_dval
Min
1
0.512
45
4
50
100
45
8
8
5
16
3
5
5
10
15
CS42438
Max
Units
-
ms
50
MHz
55
%
50
kHz
100
kHz
200
kHz
55
%
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
Notes:
17. After powering up the CS42438, RST should be held low after the power supplies and clocks are settled.
18. See Table 7 on page 43 for suggested MCLK frequencies.
19. VLS is limited to nominal 2.5 V to 5.0 V operation only.
20. ADC does not meet timing specification for Quad-Speed Mode.
FS
(input)
t_fss
SCLK
(input)
DAC_SDIN
ADC_SDOUT
t_fsh
t_sckh
t_sckl
MSB
t_ds
t_dh1
MSB
t_dh2
t_dval
MSB-1
MSB-1
Figure 5. TDM Serial Audio Interface Timing
DS646F2
21