CS42432 Datasheet, PDF (47/62 Pages) Cirrus Logic – 108 dB, 192 kHz 4-in, 6-out TDM CODEC

7.12 ADC CHANNEL INVERT (ADDRESS 17H)
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
INV_AIN4
2
INV_AIN3
1
INV_AIN2
7.12.1 INVERT SIGNAL POLARITY (INV_AINX)
Default = 0
0 - Disabled
1 - Enabled
Function:
When enabled, these bits will invert the signal polarity of their respective channels.
0
INV_AIN1
7.13 STATUS (ADDRESS 19H) (READ ONLY)
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
CLK Error
2
Reserved
1
ADC2_OVFL
0
ADC1_OVFL
For all bits in this register, a “1” means the associated error condition has occurred at least once since the register
was last read. A”0” means the associated error condition has NOT occurred since the last reading of the register.
Reading the register resets all bits to 0. Status bits that are masked off in the associated mask register will always
be “0” in this register.
7.13.1 CLOCK ERROR (CLK ERROR)
Default = x
Function:
Indicates an invalid MCLK to FS ratio. This status flag is set to “Level Active Mode” and becomes ac-
tive during the error condition. See “System Clocking” on page 31 for valid clock ratios.
7.13.2 ADC OVERFLOW (ADCX_OVFL)
Default = x
Function:
Indicates that there is an over-range condition anywhere in the CS42432 ADC signal path of each of
the associated ADC’s.
7.14 STATUS MASK (ADDRESS 1AH)
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
CLK Error_M
2
Reserved
1
0
ADC2_OVFL_M ADC1_OVFL_M
Default = 0000
Function:
The bits of this register serve as a mask for the error sources found in the register “Status (address
DS673PP2
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