CS42432 Datasheet, PDF (27/62 Pages) Cirrus Logic – 108 dB, 192 kHz 4-in, 6-out TDM CODEC

Function
ADC Soft Ramp/Zero Cross
DAC Auto-Mute
Status Interrupt
Hardware Mode Feature Summary
Default Configuration
Hardware Control
Immediate Change
-
Enabled
-
N/A
-
Note
-
-
-
5.2 Analog Inputs
Table 2. Hardware Configurable Settings
5.2.1 Line Level Inputs
AINx+ and AINx- are the line level differential analog inputs internally biased to VQ, approxi-
mately VA/2. Figure 9 on page 27 shows the full-scale analog input levels. The CS42432 also
accommodates single-ended signals on all inputs, AIN1-AIN4. See “ADC Input Filter” on
page 49 for the recommended input filters.
Hardware Mode
AIN Volume Control and ADC Overflow status are not accessible in Hardware Mode.
Software Mode
For single-ended operation on ADC1-ADC2 (AIN1 to AIN4), the ADCx_SINGLE bit in the regis-
ter “ADC Control & DAC De-emphasis (address 05h)” on page 43 must be set appropriately (see
Figure 20 on page 49 for required external components).
The gain/attenuation of the signal can be adjusted for each AINx independently through the
“AINX Volume Control (address 11h-14h)” on page 46. The ADC output data is in 2’s comple-
ment binary format. For inputs above positive full scale or below negative full scale, the ADC will
output 7FFFFFH or 800000H, respectively and cause the ADC Overflow bit in the register “Sta-
tus (address 19h) (Read Only)” on page 47 to be set to a ‘1’.
5.0 V
3.9 V
2.5 V
1.1 V
3.9 V
2.5 V
1.1 V
VA
AINx+
AINx-
Full-Scale Differential Input Level =
(AINx+) - (AINx-) = 5.6 VPP = 1.98 VRMS
Figure 9. Full-Scale Input
5.2.2 High Pass Filter and DC Offset Calibration
The high pass filter continuously subtracts a measure of the DC offset from the output of the dec-
imation filter. If the high pass filter is disabled during normal operation, the current value of the
DC offset for the corresponding channel is frozen and this DC offset will continue to be subtract-
DS673PP2
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