CS42432 Datasheet, PDF (36/62 Pages) Cirrus Logic – 108 dB, 192 kHz 4-in, 6-out TDM CODEC

Send MAP byte, auto increment off.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 10010xx1(chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
Setting the auto-increment bit in the MAP allows successive reads or writes of consecutive reg-
isters. Each byte is separated by an acknowledge bit.
5.8 Recommended Power-up Sequence
5.8.1 Hardware Mode
1) Hold RST low until the power supply and hardware control pins are stable. In this state, the
control port is reset to its default settings and VQ will remain low.
2) Bring RST high. The device will initially be in a low power state with VQ low.
3) Start MCLK to the appropriate frequency, as discussed in section 5.4 on page 31.
4) The device will initiate the hardware mode power up sequence. All features will default to the
hardware mode defaults as listed in Table 2 on page 26 according to the hardware mode control
pins. VQ will quick-charge to approximately VA/2 and the analog output bias will clamp to VQ.
5) Apply LRCK, SCLK and SDIN. Following approximately 2000 sample periods, the device is
initialized and ready for normal operation.
NOTE: During the H/W mode power up sequence, there must be no transitions on any of the
hardware control pins.
5.8.2 Software Mode
1) Hold RST low until the power supply is stable. In this state, the control port is reset to its de-
fault settings and VQ will remain low.
2) Bring RST high. The device will initially be in a low power state with VQ low. All features will
default as described in the “Register Quick Reference” on page 38.
3) Perform a write operation to the Power Control register (“Power Control (address 02h)” on
page 41) to set bit 0 to a ‘1’b. This will place the device in a power down state.
4) Load the desired register settings while keeping the PDN bit set to ‘1’b.
5) Start MCLK to the appropriate frequency, as discussed in section 5.4 on page 31. The device
will initiate the software mode power up sequence.
6) Set the PDN bit in the power control register to ‘0’b.
7) Apply LRCK, SCLK and SDIN. Following approximately 2000 sample periods, the device is
initialized and ready for normal operation.
5.9 Reset and Power-up
It is recommended that reset be activated if the analog or digital supplies drop below the recommended
operating condition to prevent power glitch related issues.
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