CS4270 Datasheet, PDF (4/48 Pages) Cirrus Logic – 24-Bit, 192 kHz Stereo Audio CODEC

CS4270
8.2 Power Control - Address 02h .......................................................................................... 34
8.2.1 Freeze (Bit 7) ...................................................................................................... 34
8.2.2 PDN_ADC (Bit 5) ................................................................................................ 34
8.2.3 PDN_DAC (Bit 1) ................................................................................................ 34
8.2.4 Power Down (Bit 0) ............................................................................................. 34
8.3 Mode Control - Address 03h ............................................................................................ 35
8.3.1 ADC Functional Mode & Master / Slave Mode (Bits 5:4) .................................... 35
8.3.2 Ratio Select (Bits 3:1) ......................................................................................... 35
8.3.3 PopGuard Disable (Bit 0) .................................................................................... 35
8.4 ADC and DAC Control - Address 04h ............................................................................. 35
8.4.1 ADC HPF Freeze A (Bit 7) .................................................................................. 35
8.4.2 ADC HPF Freeze B (Bit 6) .................................................................................. 36
8.4.3 Digital Loopback (Bit 5) ....................................................................................... 36
8.4.4 DAC Digital Interface Format (Bits 4:3) ............................................................... 36
8.4.5 ADC Digital Interface Format (Bit 0) ................................................................... 36
8.5 Transition Control - Address 05h ..................................................................................... 37
8.5.1 DAC Single Volume (Bit 7) .................................................................................. 37
8.5.2 Soft Ramp or Zero Cross Enable (Bits 6:5) ........................................................ 37
8.5.3 Invert Signal Polarity (Bits 4:1) ............................................................................ 37
8.5.4 De-Emphasis Control (Bit 0) ............................................................................... 38
8.6 Mute Control - Address 06h ............................................................................................. 38
8.6.1 Auto-Mute (Bit 5) ................................................................................................. 38
8.6.2 ADC Channel A & B Mute (Bits 4:3) ................................................................... 38
8.6.3 Mute Polarity (Bit 2) ............................................................................................ 38
8.6.4 DAC Channel A & B Mute (Bits 1:0) ................................................................... 38
8.7 DAC Channel A Volume Control - Address 07h .............................................................. 39
8.8 DAC Channel B Volume Control - Address 08h .............................................................. 39
10. PACKAGE DIMENSIONS .................................................................................................... 41
11. APPENDIX ....................................................................................................................... 42
12. REVISION HISTORY ............................................................................................................ 48
LIST OF FIGURES
Figure 1. Output Test Load ....................................................................................................................... 10
Figure 2. Maximum Loading ...................................................................................................................... 10
Figure 3. Master Mode Serial Audio Port Timing ...................................................................................... 17
Figure 4. Slave Mode Serial Audio Port Timing ........................................................................................ 17
Figure 5. Format 0, Left Justified up to 24-Bit Data .................................................................................. 18
Figure 6. Format 1, I²S up to 24-Bit Data .................................................................................................. 18
Figure 7. Format 2, Right Justified 16-Bit Data. (Available in Control Port Mode only)
Format 3, Right Justified 24-Bit Data. (Available in Control Port Mode only) ............................................ 18
Figure 8. I²C Mode Control Port Timing .................................................................................................... 19
Figure 9. SPI Control Port Timing ............................................................................................................. 20
Figure 10. CS4270 Typical Connection Diagram ...................................................................................... 21
Figure 11. De-Emphasis Curve ................................................................................................................. 27
Figure 12. CS4270 Recommended Analog Input Network ....................................................................... 28
Figure 13. CS5344 Example Analog Input Network .................................................................................. 29
Figure 14. CS4270 Recommended Analog Output Filter .......................................................................... 29
Figure 15. Suggested Active-Low Mute Circuit ......................................................................................... 30
Figure 16. Control Port Timing, SPI mode ................................................................................................ 31
Figure 17. Control Port Timing, I²C Mode ................................................................................................. 32
Figure 18. De-Emphasis Curve ................................................................................................................. 38
Figure 19. DAC Single-Speed (fast) Stopband Rejection ......................................................................... 42
Figure 20. DAC Single-Speed (fast) Transition Band ............................................................................... 42
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DS686A1