CS4270 Datasheet, PDF (35/48 Pages) Cirrus Logic – 24-Bit, 192 kHz Stereo Audio CODEC

CS4270
8.3 Mode Control - Address 03h
7
Reserved
6
Reserved
5
FM_&_M/S_
Mode1
4
3
2
1
FM_&_M/S_
Mode0
MCLK freq<2> MCLK freq<1> MCLK freq<0>
0
PopGuard
Disable
8.3.1 ADC Functional Mode & Master / Slave Mode (Bits 5:4)
Function:
In Control Port Master Mode, the user must configure the CS4270 Speed Mode with these bits. In Control
Port Slave Mode, the CS4270 auto-detects speed mode.
FM_&_M/S_ FM_&_M/S_
Mode1
Mode0
Mode
0
0
Single-Speed Mode: 4 to 54 kHz sample rates
0
1
Double-Speed Mode: 50 to 108 kHz sample rates
1
0
Quad-Speed Mode: 100 to 216 kHz sample rates
1
1
Slave Mode (default)
Table 8. Functional Mode Selection
8.3.2 Ratio Select (Bits 3:1)
Function:
These bits are used to select the clocking ratios.
MCLK freq<2>
0
0
0
0
1
MCLK freq<1>
0
0
1
1
0
MCLK freq<0>
0
1
0
1
0
Table 9. MCLK Divider Configuration
Mode
Divide by 1 (default)
Divide by 1.5
Divide by 2
Divide by 3
Divide by 4
8.3.3 PopGuard Disable (Bit 0)
Function:
Disables PopGuard when set. PopGuard is enabled by default.
8.4 ADC and DAC Control - Address 04h
7
ADC HPF
Freeze A
6
ADC HPF
Freeze B
5
Digital
Loopback
4
DAC_DIF1
3
DAC_DIF0
2
Reserved
1
Reserved
0
ADC_DIF0
8.4.1 ADC HPF Freeze A (Bit 7)
Function:
When this bit is set, the internal high-pass filter for the selected channel will be disabled.The current DC
offset value will be frozen and continuously subtracted from the conversion result. Section 5.2.7 “High-
Pass Filter and DC Offset Calibration” on page 26.
DS686A1
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