CS4270 Datasheet, PDF (20/48 Pages) Cirrus Logic – 24-Bit, 192 kHz Stereo Audio CODEC

CS4270
SWITCHING CHARACTERISTICS - SPI CONTROL PORT
(Inputs: logic 0 = DGND, logic 1 = VLC)
Parameter
SPI Mode
CCLK Clock Frequency
RST Rising Edge to CS Falling
CCLK Edge to CS Falling
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
Symbol
Min
f_sclk
-
t_srs
500
(Note 19)
t_spi
500
t_csh
1.0
t_css
20
t_scl
82
t_sch
82
t_dsu
40
(Note 20)
t_dh
15
(Note 21)
t_r2
-
(Note 21)
t_f2
-
Max
6
-
-
-
-
-
-
-
-
100
100
Unit
MHz
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
19. t_spi only needed before first falling edge of CS after RST rising edge. t_spi = 0 at all other times.
20. Data must be held for sufficient time to bridge the transition time of CCLK.
21. For F_SCK < 1 MHz
RST
t _srs
CS
t _spi t _css
t _scl t _sch
t _csh
CCLK
t _r2
t _f2
CDIN
t _{dsu t dh}
Figure 9. SPI Control Port Timing
20
DS686A1