CS4270 Datasheet, PDF (32/48 Pages) Cirrus Logic – 24-Bit, 192 kHz Stereo Audio CODEC

CS4270
6.2 I²C Mode
In I²C mode, SDA is a bi-directional data line. Data is clocked into and out of the part by the clock, SCL, with
the clock to data relationship as shown in Figure 17. There is no CS pin. Pins AD0, AD1, and AD2 form the
partial chip address and should be tied to VLC or DGND as required. The upper 4 bits of the 7-bit address
field must be 1001. To communicate with the CS4270, the three lower bits of the chip address field should
match the setting on the AD0, AD1, and AD2 pins. The eighth bit of the address byte is the R/W bit (high for
a read, low for a write). The next byte is the Memory Address Pointer, MAP, which selects the register to be
read or written. If the operation is a write, the MAP is then followed by the data to be written. If the operation
is a read, then the contents of the register pointed to by the MAP will be output after the chip address.
The CS4270 has MAP auto increment capability, enabled by the INCR bit in the MAP. If INCR is 0, then the
MAP will stay constant for successive writes. If INCR is set, then MAP will auto increment after each byte
is written, allowing block reads or writes of successive registers.
SDA
1001
ADDR
AD2 - AD0
R/W
ACK
Note 1
DATA
1-8
ACK
DATA
1-8
ACK
SCL
Start
Stop
Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.
Figure 17. Control Port Timing, I²C Mode
7
6
5
4
3
INCR
Reserved
Reserved
Reserved
MAP3
0
0
0
0
0
INCR - Auto MAP Increment Enable
Default = ‘0’.
0 - Disabled
1 - Enabled
MAP(3:0) - Memory Address Pointer
Default = ‘0000’.
Table 7. Memory Address Pointer
2
MAP2
0
1
MAP1
0
0
MAP0
0
32
DS686A1