CS4360_04 Datasheet, PDF (35/37 Pages) Cirrus Logic – 24-Bit, 192 kHz 6 Channel D/A Converter

CS4360
6.5.5
FREEZE CONTROLS (FREEZE) BIT 2
Default = 0
0 - Disabled
1 - Enabled
Function:
This function allows modifications to be made to the registers without the changes taking effect until
the FREEZE is disabled. To have multiple changes in the control port registers take effect simulta-
neously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit.
6.5.6
MASTER CLOCK DIVIDE ENABLE (MCLKDIV) BIT 1
Default = 0
0 - Disabled
1 - Enabled
Function:
The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all
other internal circuitry.
6.5.7
SINGLE VOLUME CONTROL (SNGLVOL) BIT 0
Default = 0
0 - Disabled
1 - Enabled
Function:
The individual channel volume levels are independently controlled by their respective Volume Control
Bytes when this function is disabled. When enabled, the volume on all channels is determined by the
A1 Channel Volume Control Byte, and the other Volume Control Bytes are ignored.
6.6 REVISION REGISTER (READ ONLY) (ADDRESS 0DH)
7
Reserved
0
6
Reserved
0
5
Reserved
0
4
Reserved
0
3
REV3
X
2
REV2
X
1
REV1
X
0
REV0
X
6.6.1
REVISION INDICATOR (REV) [READ ONLY] BIT 0-3
Default = none
0001 - Revision A
0010 - Revision B
0011 - Revision C
etc.
Function:
This read-only register indicates the revision level of the device.
DS517F2
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