CS4360_04 Datasheet, PDF (17/37 Pages) Cirrus Logic – 24-Bit, 192 kHz 6 Channel D/A Converter

CS4360
SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE
Inputs: Logic 0 = GND, Logic 1 = VLC
Parameter
Symbol
Min
I²C Mode
SCL Clock Frequency
f_scl
-
RST Rising Edge to Start
t_irs
500
Bus Free Time Between Transmissions
t_buf
4.7
Start Condition Hold Time (prior to first clock pulse)
t_hdst
4.0
Clock Low time
t_low
4.7
Clock High Time
t_high
4.0
Setup Time for Repeated Start Condition
t_sust
4.7
SDA Hold Time from SCL Falling
(Note 7)
t_hdd
0
SDA Setup time to SCL Rising
t_sud
250
Rise Time of SCL and SDA
t_rc, t_rc
-
Fall Time SCL and SDA
t_fc, t_fc
-
Setup Time for Stop Condition
t_susp
4.7
Acknowledge Delay from SCL Falling
(Note 8)
t_ack
-
Max
Unit
100
kHz
-
ns
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
-
ns
1
µs
300
ns
-
µs
(Note 9)
ns
Notes: 7. Data must be held for sufficient time to bridge the transition time, t_fc, of SCL.
8. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.
9. _{----------5----------} for Single-Speed Mode, _{----------5----------} for Double-Speed Mode, _{--------5---------} for Quad-Speed Mode.
256 × Fs
128 × Fs
64 × Fs
RST
t _irs
S to p
S ta rt
SDA
SCL
t _buf
t _hdst
t _high
t
lo w
t
hdd
t _sud t _ack
R e pe ate d
S ta rt _{t rd}
t _hdst
S to p
t _fd
t _fc
t _susp
t _sust
t _rc
Figure 13. Control Port Timing - I²C Mode
DS517F2
17