WM8321 Datasheet, PDF (34/253 Pages) Wolfson Microelectronics plc – Processor Power Management Subsystem

WM8321
ADDRESS
BIT
LABEL
1
RESET_HW
0
RESET_WDOG
R16399
(400Fh)
OFF Source
13 OFF_INTLDO_ERR
12 OFF_PWR_SEQ
11 OFF_GPIO
10 OFF_PVDD
9
OFF_THERR
6
OFF_SW_REQ
4
OFF_ON_PIN
Table 2 Power State Control Registers
Production Data
DEFAULT
0
0
0
0
0
0
0
0
0
DESCRIPTION
Most recent ON event type
0 = Not caused by Hardware
Reset
1 = Caused by Hardware Reset
Most recent ON event type
0 = Not caused by the Watchdog
1 = Caused by a Device Reset
triggered by the Watchdog timer
Most recent OFF event type
0 = Not caused by LDO13 Error
condition
1 = Caused by LDO13 Error
condition
Most recent OFF event type
0 = Not caused by Power
Sequence Failure
1 = Caused by a Power Sequence
Failure
Most recent OFF event type
0 = Not caused by GPIO input
1 = Caused by GPIO input
Most recent OFF event type
0 = Not caused by PVDD
1 = Caused by the SYSLO or
SHUTDOWN threshold
Most recent OFF event type
0 = Not caused by temperature
1 = Caused by over-temperature
Most recent OFF event type
0 = Not caused by software OFF
1 = Caused by software OFF
command (CHIP_ON = 0)
Most recent OFF event type
0 = Not caused by the ON pin
1 = Caused by the ON pin
Table 3 lists all of the events which can trigger an ON, WAKE, OFF or SLEEP transition sequence. It
also lists the associated status bits of the ‘ON Source’ and ‘OFF Source’ register bits which are
asserted under each condition.
w
PD, February 2012, Rev 4.0
34