WM8321 Datasheet, PDF (150/253 Pages) Wolfson Microelectronics plc – Processor Power Management Subsystem

WM8321
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
8 OTP_READ
7:6 OTP_READ_L
VL [1:0]
5 OTP_BULK
1:0 OTP_PAGE
[1:0]
0
Selects READ command for the selected memory
page(s).
0 = No action
1 = Read Command
Protected by security key.
00
Selects the Margin Level for READ or VERIFY OTP
commands.
00 = Normal
01 = Reserved
10 = Margin 1
11 = Margin 2
Protected by security key.
0
Selects the number of memory pages for ICE / OTP
commands.
0 = Single Page
1 = All Pages
00
Selects the single memory page for ICE / OTP
commands (when OTP_BULK=0).
If OTP is selected (OTP_MEM = 1):
00 = Page 0
01 = Page 1
10 = Page 2
11 = Page 3
Register 400Ah OTP Control
If ICE is selected (OTP_MEM = 0):
00 = Page 2
01 = Page 3
10 = Page 4
11 = Reserved
Production Data
REFER TO
REGISTER
ADDRESS
R16396
(400Ch)
GPIO Level
BIT
LABEL
11 GP12_LVL
10 GP11_LVL
9 GP10_LVL
DEFAULT
DESCRIPTION
REFER TO
0
GPIO12 level.
When GP12_FN = 0h and GP12_DIR = 0, write to this
bit to set a GPIO output.
Read from this bit to read GPIO input level.
When GP12_POL is 0, the register contains the
opposite logic level to the external pin.
0
GPIO11 level.
When GP11_FN = 0h and GP11_DIR = 0, write to this
bit to set a GPIO output.
Read from this bit to read GPIO input level.
When GP11_POL is 0, the register contains the
opposite logic level to the external pin.
0
GPIO10 level.
When GP10_FN = 0h and GP10_DIR = 0, write to this
bit to set a GPIO output.
Read from this bit to read GPIO input level.
When GP10_POL is 0, the register contains the
opposite logic level to the external pin.
w
PD, February 2012, Rev 4.0
150