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| CS4294 Datasheet, PDF (33/42 Pages) Cirrus Logic – SoundFusion Audio/Docking Codec 97 (AMC 97) | |||
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8. PIN DESCRIPTIONS
CS4294
GPIO3
DVdd1
XTL_OUT
XTL_IN
DVss1
SDATA_OUT
BIT_CLK
DVss2
SDATA_IN
DVdd2
SYNC
RESET#
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
CS4294-XQ
29
9
10
48-Pin TQFP
28
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
AVdd3
ID0#
ALT_LINE_OUT_R
ALT_LINE_OUT_L
AVss2
AVdd2
LINE_OUT_R
LINE_OUT_ L
ID1#
AFLT2
AFLT1
Vrefout
8.1 Digital I/O Pins
RESET# - AC â97 Chip Reset, Input
This active low signal is the asynchronous Cold Reset input to the CS4294. The CS4294 must
be reset before it can enter normal operating mode. When the PR4 bit of register 26h is set, the
RESET# rising edge will be used as an AC â97 2.1 Warm Reset only, preserving register
values.
SYNC - AC-link Serial Port Sync pulse, Input
This signal is the serial port timing signal for the AC-link of the CS4294. Its period is the
reciprocal of the sample rate of the CS4294, 48 kHz. This signal is generated by the AC â97
Controller and is synchronous to BIT_CLK. SYNC is also an asynchronous input when the
CS4294 is in a PR4 powerdown state and is configured as a primary codec. A series
terminating resistor of 47 ⦠should be connected on this signal close to the device driving the
signal.
DS326PP4
33
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