CS4294 Datasheet, PDF (12/42 Pages) Cirrus Logic – SoundFusion Audio/Docking Codec 97 (AMC 97)

CS4294
4.1 Audio Output Mixer
The stereo output mixer sums together the analog
outputs from the Input Mixer, stereo enhancement,
and the PCM DAC output. The stereo output mix is
sent to the LINE_OUT and ALT_LINE_OUT out-
put pins of the CS4294. When the device is set to
Mode 1 or the EAM bit in AC Mode Control (Index
5Eh) is set, the secondary DAC outputs are routed
to ALT_LINE_OUT.
4.2 Audio Input Mux
The input multiplexer controls which analog input
is sent to the ADCs. The output of the input mux is
converted to stereo 18-bit digital PCM data and
sent to the Digital Controller chip in Slots 3 and 4
of the AC-Link SDATA_IN signal.
4.3 Audio Input Mixer
The input mixer is an analog mix of the analog in-
put signals such as MIC, LINE_IN, etc., and the
PCM Audio DAC output. The output of the mixer
is routed to the ADC Input Mux, Audio Output
Mixer, and may be routed to the Extended Audio
ADC input.
4.4 Audio Volume Control
The volume control registers of the AC ’97 Regis-
ter interface control analog input level to the input
mixer, the master volume level, and the alternate
volume level. All analog volume controls imple-
ment volume steps at nominally 1.5 dB per step.
The analog inputs allow a mixing range of +12 dB
of signal gain to -34.5 dB of signal attenuation. The
analog output volume controls allows from 0 dB to
-94.5 dB of attenuation.
5. AC ‘97
5.1 AC ‘97 Frame Definition
The AC Link is a bi-directional serial port with
thirteen time-division multiplexed slots in each di-
rection. The first slot is 16 bits long and termed the
tag slot. Bits in the tag slot determine if the Codec
is ready and indicate which, if any, other slots con-
tain valid data. Slots 1 through 11 are 20-bits long
and can contain audio data. Slot 12 contains data to
be written and read from GPIO. The serial data line
is defined from the Controller’s perspective, NOT
from the Audio Codec’s perspective.
5.2 AC-Link Serial Data Output Frame
In the serial data output frame, data is passed on the
SDATA_OUT pin TO the CS4294 FROM the
Controller. Figure 9 illustrates the serial port tim-
ing.
Tag Phase
SYNC
BIT_CLK
12.288 MHz
81.4 nS
20.8 µS
(48 kHz)
Data Phase
Bit Frame Position: F255
SDATA_OUT X
F0
Valid
Frame
F1
Slot 1
Valid
F2
Slot 2
Valid
F12
F13
F14 F15
F16
0
0 SCRA1 SCRA0 R/W
F35
F36
F56
F57
F76
F97
F255
0 WD15
LP19 LP18
RP19
X
X
Bit Frame Position: F255
SDATA_IN
0
F0
Codec
Ready
F1
Slot 1
Valid
F2
Slot 2
Valid
F12
F13
F14 F15
F16
0
0
0
0
0
F35
F36
F56 F57
F76
F97
F255
0 RD15
LC17 LC16
RC17
0
0
Slot 0
Slot 1
Slot 2
Slot 3
Figure 9. AC-link Input and Output Framing
Slot 4
Slots 5-12
12
DS326PP4