CS4294 Datasheet, PDF (17/42 Pages) Cirrus Logic – SoundFusion Audio/Docking Codec 97 (AMC 97)

CS4294
6. REGISTER INTERFACE
Certain register locations change definition based on the basic operating mode (Mode 0,1) selected by the
MD[1:0] bits found in the AC Mode Control (Index 5Eh) register. The reset default is Mode 0.
Reg
Num
Name
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
00h Reset
Mode 0
00h Reset
Mode 1
02h Master Volume
Mute
04h Alternate Line Out Volume Mute
0Eh Mic Volume
Mute
10h Line In Volume
Mute
12h CD Volume
Mute
16h Aux Volume
Mute
18h PCM Out Vol
Mute
1Ah Record Select
1Ch Record Gain
Mute
20h General Purpose
POP
22h Stereo Enhancement
26h Powerdown Ctrl/Stat
28h Ext’d Audio ID Mode 0 ID1
28h Ext’d Audio ID Mode 1 ID1
2Ah
Ext’d Audio Stat/Ctrl Mode
0
2Ah
Ext’d Audio Stat/Ctrl Mode
1
2Ch PCM Front DAC Rate
SR15
2Eh PCM Surround DAC Rate SR15
30h PCM LFE DAC Rate
SR15
32h PCM Left/Right ADC Rate SR15
36h Center LFE Volume
Mute
38h LR Surround Volume
Mute
3Ch Ext’d Codec ID
ID1
3Eh
Ext’d Codec Stat/Ctrl
Mode 0
PRH
3Eh
Ext’d Codec Stat/Ctrl
Mode 1
40 Ext’d DAC1/ADC1 Rate SR15
44 Ext’d DAC2/ADC2 Rate SR15
46 Ext’d DAC1/ADC1 Level Mute
4A Ext’d DAC2/ADC2 Level Mute
4C GPIO Pin Configuration
4E GPIO Pin Polarity/Type
50 GPIO Pin Sticky
52 GPIO Pin Wakeup Mask
54 GPIO Pin Status
Cirrus Defined Registers:
5A Crystal Revision / Fab
5E Slot Map Register
7Ch Vendor ID1(CR)
F7
7Eh Vendor ID2(Y-)
T7
SE4 SE3 SE2 SE1 SE0 0
SE4 SE3 SE2 SE1 SE0 0
ML5 ML4 ML3 ML2 ML1
ML5 ML4 ML3 ML2 ML1
GL4 GL3 GL2 GL1
GL4 GL3 GL2 GL1
GL4 GL3 GL2 GL1
GL4 GL3 GL2 GL1
SL2 SL1
GL3 GL2 GL1
SEE
PR6 PR5 PR4 PR3 PR2 PR1
ID0
ID0
PRK PRJ PRI
SR14 SR13 SR12 SR11 SR10 SR9
SR14 SR13 SR12 SR11 SR10 SR9
SR14 SR13 SR12 SR11 SR10 SR9
SR14 SR13 SR12 SR11 SR10 SR9
LFE5 LFE4 LFE3 LFE2 LFE1
LSR5 LSR4 LSR3 LSR2 LSR1
ID0
PRG
PRD PRC PRB
PRG
PRC PRB
SR14 SR13 SR12 SR11 SR10 SR9
SR14 SR13 SR12 SR11 SR10 SR9
DAC3 DAC2 DAC1
DAC3 DAC2 DAC1
1
EDM EAM
F6 F5 F4 F3 F4 F1
T6 T5 T4 T3 T2 T1
ID8
ID8
ML0
ML0
GL0
GL0
GL0
GL0
SL0
GL0
PR0
ID7 0
ID7 0
20dB
LPBK
0
0
MR5
MR5
ID4
0
MR4
MR4
GN4
GR4
GR4
GR4
GR4
0
0
MR3
MR3
GN3
GR3
GR3
GR3
GR3
GR3
S3
REF
0
0
MR2
MR2
GN2
GR2
GR2
GR2
GR2
SR2
GR2
S2
ANL
0
0
MR1
MR1
GN1
GR1
GR1
GR1
GR1
SR1
GR1
S1
DAC
LDAC SDAC CDAC
LDAC SDAC CDAC
SR8 SR7 SR6
SR8 SR7 SR6
SR8 SR7 SR6
SR8 SR7 SR6
LFE0 Mute
LSR0 Mute
SR5 SR4 SR3 SR2 SR1
SR5 SR4 SR3 SR2 SR1
SR5 SR4 SR3 SR2 SR1
SR5 SR4 SR3 SR2 SR1
CNT5 CNT4 CNT3 CNT2 CNT1
RSR5 RSR4 RSR3 RSR2 RSR1
PRA
EDAC EADC
2
2
PRA
EADC
2
SR8 SR7 SR6 SR5
SR8 SR7 SR6 SR5
DAC0 Mute
DAC0 Mute
GC8 GC7 GC6 GC5
GP8 GP7 GP6 GP5
GS8 GS7 GS6 GS5
GW8 GW7 GW6 GW5
Gi8 GI7 GI6 GI5
SR4
SR4
GC4
GP4
GS4
GW4
GI4
EDA
C1
EAD
C1
EREF
EAD
C1
EREF
SR3 SR2 SR1
SR3 SR2 SR1
ADC3 ADC2
ADC3 ADC2
GC3
GP3
GS3
GW3
GI3
1
DDM
F0 S7
T0 0
S6 S5 S4 S3
PID2 PID1 PID0 1
S2
RID2
1
MD1
S1
RID1
0
0
MR0
MR0
GN0
GR0
GR0
GR0
GR0
SR0
GR0
S0
ADC
VRA
VRA
1990h
1980h
8000h
8000h
8008h
8808h
8808h
8808h
8808h
0000h
8000h
0000h
0000h
000Fh
x000h
x1C0h
0000h
01C0h
SR0 BB80h
SR0 BB80h
SR0 BB80h
SR0 BB80h
CNT0 8080h
RSR0 8080h
x005h
GPIO 00CFh
GPIO 0047h
SR0 BB80h
SR0 BB80h
8080h
8080h
03FFh
FFFFh
0000h
0000h
xxxxh
0
MD0
S0
RID0
0302h
0000h
4352h
5923h
Table 1. Mixer Registers
DS326PP4
17