CS4294 Datasheet, PDF (22/42 Pages) Cirrus Logic – SoundFusion Audio/Docking Codec 97 (AMC 97)

CS4294
6.1.10 Power Down Control/Status (Index 26h)
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
PR6 PR5 PR4 PR3 PR2 PR1 PR0
REF ANL DAC ADC
PR6
PR5
PR4
PR3
PR2
PR1
PR0
REF
ANL
DAC
ADC
Default
When set, the alternate line-out buffer is powered down.
When set, the internal master clock is disabled. The only way to recover from setting this bit is through
a cold AC ‘97 reset (driving the RESET# signal active).
When set, the AC link is powered down. The AC link can be restarted through a warm AC ‘97 reset using
the SYNC signal, or a cold AC ‘97 reset using the RESET# signal (the primary codec only).
When set, the analog mixer and voltage reference are powered down. When clearing this bit, the ANL,
ADC, and DAC bits should be checked before writing any mixer registers. Because the reference volt-
age is shared with the extended audio subsection, it will not power down unless the PRB bit is also set
in the Extended Codec Stat/Ctrl (Index 3Eh) register.
When set, the analog mixer is powered down (the voltage reference is still active). When clearing this
bit, the ANL bit should be checked before writing any mixer registers.
When set, the DACs are powered down. When clearing this bit, the DAC bit should be checked before
sending any data to the DACs.
When set, the ADCs and the ADC input muxes are powered down. When clearing this bit, no valid data
will be sent down the AC link until the ADC bit goes high.
Voltage Reference Ready Status. When set, indicates the voltage reference is at a nominal level.
Analog Ready Status. When set, the analog output mixer, input multiplexer, and volume controls are
ready. When clear, no volume control registers should be written.
DAC Ready Status. When set, the DACs are ready to receive data across the AC link. When clear, the
DACs will not accept any valid data.
ADC Ready Status. When set, the ADCs are ready to send data across the AC link. When clear, no data
will be sent to the Controller.
0000h, all blocks are powered on. The lower four bits will eventually change as the Codec finishes an
initialization and calibration sequence.
The PR[6:0] are power-down control for different sections of the Codec. The REF, ANL, DAC, and
ADC bits are status bits which, when set, indicate that a particular section of the Codec is ready. After
the Controller receives the Codec Ready bit in Slot 0, these status bits must be checked before writing
to any mixer registers.
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