CS22220 Datasheet, PDF (32/34 Pages) Cirrus Logic – WIRELESS PCI/USB CONTROLLER

Table 15. Radio MAC AC Timings – Intersil Modes
Parameter
t_dBBAS
t_dBBRNW
t_dnBBCS
t_dBBSDX
T_suBBSDX
T_hBBSDX
t_dTXD
t_dTXD
T_suRXD
T_hRXD
T_suMDRDY
T_hMDRDY
t_dTXPEBB
t_dRXPEBB
T_suTXRDY
T_hTXRDY
T_dutyRXCLK ²
T_dutyTXCLK ²
Parameter Description
Min
Max
BBAS output delay from falling BBSCLK
8.2
BBRNW output delay from falling BBSCLK
8.0
nBBCS output delay from falling BBSCLK
59.0
BBSDX output delay from falling BBSCLK
7.0
BBSDX setup to rising edge of BBSCLK
14.8
BBSDX hold from rising edge of BBSCLK
0.0
TXD output delay from rising TXCLK (SMAC
33.5
Mode)
TXD output delay from rising TXCLK (RMAC
15.4
Mode)
RXD setup to rising edge of RXCLK
1.0
RXD hold from rising edge of RXCLK
1.8
MDRDY setup to falling edge of RXCLK
2
MDRDY hold from falling edge of RXCLK
1
TXPEBB output delay from rising TXCLK
15.0
RXPEBB output delay from rising RXCLK
16.0
TXRDY setup to falling edge of TXCLK
6.5
TXRDY hold from falling edge of TXCLK
0
RXCLK period
See Note
TXCLK period
See Note
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1.
2.
3.
4.
5.
CCA signal is double synchronized to ARMCLKIN.
ARMCLK must be at least 4 times the TXCLK and RXCLK frequency.
Harris baseband (3824/3824A) generates RXCLK and TXCLK of 4 Mhz. the duty cycle varies between 33-40%
with a high time of 90.9ns and low time that alternates between 136 and 182ns. The clock period varies between
227 and 272 ns, giving an effective period of 250ns.
TXD delay in 802.11b mode is the result of sampling the TXCLK with the ctlclk, therefore the maximum delay
is equal to two ctlclk periods plus the flop-to-output delay. In this table, ctlclk is assumed to have a 13 ns
period.
BBNCS output delay = [(1/ARMCLK freq)*ceiling(SER_CLK_DIV/2)] + 7ns, the specified value is based on
ARMCLK of 77 Mhz and SER_CLK_DIV=8.
CS22220 Wireless PCMCIA Controller
32 of 34
www.cirrus.com
DS557PP2 Rev. 3.0