CS22220 Datasheet, PDF (26/34 Pages) Cirrus Logic – WIRELESS PCI/USB CONTROLLER

Table 8. ROM/Flash Memory ‘Read’ Timing
Item
Clock Period ⁽¹⁾
CE to SMD Latched Data ⁽²⁾
OE de-asserted to OE asserted ⁽³⁾
ROM address to output delay ⁽⁴⁾
SMCLK to SMA output delay
SMCLK to BRCE output delay (CE)
SMCLK to SMRAS output delay (OE)
SMD setup to SMCLK
SMD hold from SMCLK
Symbol
t_perSMCLK
t_id SMD
t_f SMRAS
t_ACC
t_d SMA
t_d BRCE
t_d SMRAS
t_su SMD
t_h SMD
Min
72 MHz
6(t_perSMCLK)
1.0 ns
2.4 ns
Max
103 MHz
221 ns
220 ns
4.0 ns
4.5 ns
5.0 ns
1. The memclock timing is derived by bootstrap PLL settings. Synchronous modes at 77 MHz & 72
MHz are currently supported.
2. t_id SMD is based on the fm_romrdlat register settings – default is 09h max. (77Mhz ~ 17 times
SMCLK = 221ns).
3. t_f SMRAS is the minimum time required before the next OE is active on the bus (6 times SMCLK).
The ROM device must release the bus within this time frame (77MHz ~ 78 ns).
4. Based on default fm_romrdlat register settings (note: 09h translates to 11h) see fm_romrdlat register
settings for more information)
t_pe^S_r ^MCLK
SMCLK
SMD[7:0]
SMA[11:0], SMD[13:8]
t _ACC
t_d^SMA
t
SMD
ld
t_s^S_u^MD
t
SMD
h
DATA
ADDRESS
SMNWE
BRCE (CE)
SMRAS (OE)
t_d^BRCE
t_d^SMRAS
t
SMRAS
f
t_d^BRCE
t_d^SMRAS
Figure 7. ROM Memory Interface 'Read' Timing Diagram
CS22220 Wireless PCMCIA Controller
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