CS22220 Datasheet, PDF (24/34 Pages) Cirrus Logic – WIRELESS PCI/USB CONTROLLER

5.1 AC Characteristics and Timing
Table 7. System Memory Interface Timings
Parameter
t_dSMD
t_dSMA
t_dSMDQM
t_dSMNCS
t_dSMNWE
t_dSMCKE
t_dSMNCAS
t_dSMNRAS
T_perSMCLK
T_suSMD
T_hSMD
Parameter Description
SMCLK to SMD[31:0] output delay
SMCLK to SMA[11:0] output delay
SMCLK to SMDQM[3:0] output delay
SMCLK to SMNCS[1:0] output delay
SMCLK to SMNWE output delay
SMCLK to SMCKE output delay
SMCLK to SMNCAS output delay
SMCLK to SMNRAS output delay
SMCLK period
SMD[31:0] setup to SMCLK
SMD[31:0] hold from SMCLK
Min
Max Units
7
ns
4.7
ns
5.1
ns
4.1
ns
4.5
ns
4.3
ns
4.0
ns
5.0
ns
72
103
ns
1.0
ns
2.4
ns
Notes:
1. Outputs are loaded with 35pf on SMD, 25pf on SMA, SMDQM, SMNRAS, and SMNCAS and 20pf on SMCLK,
SMNCS, and SMCKE.
2. An attempt has been made to balance the setup time needed by the SDRAM and the setup needed by CS22210 to
read data. If there is a problem meeting setup on the SDRAM, there is a programmable delay line on SMCLK which
can help meet the setup time. Care must be taken, however, not to violate the setup on the return read data. The
delay can be increased by a multiple of 0.25ns by using the SMA[11:09] pins to selectively set the clock delay .
SMCLK
SMD[15:0]
SMA[13:0]
SMDQM[1:0]
SMNCS[1:0]
SMNWE
SMCKE
SMNRAS
SMNCAS
t_dSMA
t_dSMD
WRITE DATA
ROW ADDR
COLUMN ADDR
t_dSMDQM
t_dSMNCS
t_dSMNWE
t_dSMCKE
t_dSMNRAS
t_dSMNCAS
Figure 5. System Memory Interface ‘Write’ Timing Diagram
CS22220 Wireless PCMCIA Controller
24 of 34
www.cirrus.com
DS557PP2 Rev. 3.0