CS4362A_08 Datasheet, PDF (30/50 Pages) Cirrus Logic – 114 dB, 192 kHz 6-Channel D/A Converter

CS4362A
instructions followed by step 1 of the I²C Read section. If no further reads from other registers are de-
sired, initiate a STOP condition to the bus.
Note 1
SDA
001100 ^ADDR
AD0
R/W ACK
DATA
1-8
ACK
DATA
1-8
ACK
SCL
S ta rt
Stop
N ote: If operation is a w rite, this byte contains the M em ory A ddress Pointer, M A P.
Figure 17. Control Port Timing, I²C Mode
4.14.3 SPI Mode
In SPI Mode, data is clocked into the serial control data line, CDIN, by the serial Control Port clock, CCLK
(see Figure 18 for the clock-to-data relationship). There is no AD0 pin. Pin CS is the chip select signal and
is used to control SPI writes to the Control Port. When the device detects a high-to-low transition on the
AD0/CS pin after power-up, SPI Mode will be selected. All signals are inputs and data is clocked in on the
rising edge of CCLK.
4.14.3.1 SPI Write
To write to the device, follow the procedure below while adhering to the Control Port Switching Specifica-
tions in Section 2.
1. Bring CS low.
2. The address byte on the CDIN pin must then be 00110000.
3. Write to the memory address pointer, MAP. This byte points to the register to be written.
4. Write the desired data to the register pointed to by the MAP.
5. If the INCR bit (see Section 4.14.1) is set to 1, repeat the previous step until all the desired registers
are written, then bring CS high.
6. If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is necessary to bring
CS high, and follow the procedure detailed from step 1. If no further writes to other registers are de-
sired, bring CS high.
CS
CCLK
C D IN
CHIP
ADDRESS
MAP
DATA
0011000
R/W
MSB
LSB
byte 1 byte n
M AP = M em ory Address Pointer
Figure 18. Control Port Timing, SPI Mode
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