CS4362A_08 Datasheet, PDF (21/50 Pages) Cirrus Logic – 114 dB, 192 kHz 6-Channel D/A Converter

CS4362A
4. APPLICATIONS
The CS4362A serially accepts two’s-complement formatted PCM data at standard audio sample rates including 48,
44.1, and 32 kHz in SSM, 96, 88.2, and 64 kHz in DSM, and 192, 176.4, and 128 kHz in QSM. Audio data is input
via the serial data input pins (SDINx). The Left/Right Clock (LRCK) determines which channel is currently being input
on SDINx, and the Serial Clock (SCLK) clocks audio data into the input data buffer.
The CS4362A can be configured in Hardware Mode by the M0, M1, M2, M3, and DSD_EN pins and in Software
Mode through I²C or SPI.
4.1 Master Clock
MCLK/LRCK must be an integer ratio as shown in Table 1. The LRCK frequency is equal to Fs, the frequen-
cy at which words for each channel are input to the device. The MCLK-to-LRCK frequency ratio is detected
automatically during the initialization sequence by counting the number of MCLK transitions during a single
LRCK period. Internal dividers are then set to generate the proper internal clocks. Table 1 illustrates several
standard audio sample rates and the required MCLK and LRCK frequencies. Please note there is no re-
quired phase relationship, but MCLK, LRCK, and SCLK must be synchronous.
Speed Mode
(sample-rate range)
Sample
Rate
(kHz)
MCLK Ratio
Single-Speed
32
(4 to 50 kHz)
44.1
48
MCLK Ratio
Double-Speed
64
(50 to 100 kHz)
88.2
96
MCLK Ratio
Quad-Speed
176.4
(100 to 200 kHz)
192
256x
8.1920
11.2896
12.2880
128x
8.1920
11.2896
12.2880
64x
11.2896
12.2880
MCLK (MHz)
384x
12.2880
16.9344
18.4320
192x
12.2880
16.9344
18.4320
96x
16.9344
18.4320
512x
16.3840
22.5792
24.5760
256x
16.3840
22.5792
24.5760
128x
22.5792
24.5760
768x
24.5760
33.8688
36.8640
384x
24.5760
33.8688
36.8640
192x
33.8688
36.8640
Note: These modes are only available in Software Mode by setting the MCLKDIV bit = 1.
Table 1. Common Clock Frequencies
Software
Mode Only
1024x*
32.7680
45.1584
49.1520
512x*
32.7680
45.1584
49.1520
256x*
45.1584
49.1520
4.2 Mode Select
In Hardware Mode, operation is determined by the Mode Select pins. The states of these pins are continu-
ally scanned for any changes; however, the mode should only be changed while the device is in reset
(RST pin low) to ensure proper switching from one mode to another. These pins require connection to sup-
ply or ground as outlined in Figure 6. VLC supplies M0, M1, and M2. VLS supplies M3 and DSD_EN.
Tables 2 - 4 show the decode of these pins.
In Software Mode, the operational mode and data format are set in the FM and DIF registers. See “Digital
Interface Format (DIF)” on page 34 and “Functional Mode (FM)” on page 40.
DS617F1
21