CS4330 Datasheet, PDF (3/38 Pages) Cirrus Logic – 8 Pin Stereo D/A Converter for Digital Audio

CS4330, CS4331, CS4333
SWITCHING CHARACTERISTICS (TA = 25 °C; VA+ = 2.7V - 5.5V; Inputs: Logic 0 = 0V, Logic
1 = VA+, CL = 20 pF) Switching characteristics are guaranteed by characterization.
Parameter
Symbol
Min
Typ
Max
Units
Input Sample Rate
Fs
2
-
50
kHz
LRCK Duty Cycle (External SCLK only)
(Note 5)
30
50
70
%
MCLK Pulse Width High
MCLK / LRCK = 512
10
-
1000
ns
MCLK Pulse Width Low
MCLK / LRCK = 512
15
-
1000
ns
MCLK Pulse Width High
MCLK / LRCK = 384
21
-
1000
ns
MCLK Pulse Width Low
MCLK / LRCK = 384
21
-
1000
ns
MCLK Pulse Width High
MCLK / LRCK = 256
35
-
1000
ns
MCLK Pulse Width Low
MCLK / LRCK = 256
39
-
1000
ns
External SCLK Mode
SCLK Pulse Width Low
SCLK Pulse Width High
SCLK Period
tsclkl
20
-
tsclkh
20
-
tsclkw
1
(128)Fs
-
-
ns
-
ns
-
ns
SCLK rising to LRCK edge delay
SCLK rising to LRCK edge setup time
SDATA valid to SCLK rising setup time
SCLK rising to SDATA hold time
Internal SCLK Mode
tslrd
20
-
-
ns
tslrs
20
-
-
ns
tsdlrs
20
-
-
ns
tsdh
20
-
-
ns
SCLK Period
(Note 6) tsclkw
1
SCLK
-
-
ns
SCLK rising to LRCK edge
SDATA valid to SCLK rising setup time
tsclkr
-
t_sclkw
-
2
µs
tsdlrs
1
(512)Fs
+
15
-
-
ns
SCLK rising to SDATA hold time MCLK / LRCK = 256 or 512 tsdh
1
(512)Fs
+15
-
-
ns
SCLK rising to SDATA hold time
MCLK / LRCK = 384 tsdh
1
(384)Fs
+15
-
-
ns
Notes: 5. In Internal SCLK Mode, the Duty Cycle must be 50% ±1/2 MCLK Period.
6. The SCLK / LRCK ratio may be either 32, 48, or 64.
DS136F1
3