CS4330 Datasheet, PDF (24/38 Pages) Cirrus Logic – 8 Pin Stereo D/A Converter for Digital Audio

CDB4330, CDB4331, CDB4333
CDB4330/31/33 System Overview
The CDB4330/31/33 evaluation board is an ex-
cellent means of quickly evaluating the
CS4330/31/33. The CS8412 digital audio inter-
face receiver provides an easy interface to digital
audio signal sources including the majority of
digital audio test equipment. The evaluation
board also allows the user to supply clocks and
data through a 10-pin header for system develop-
ment.
The CDB4330/31/33 schematic has been parti-
tioned into 5 schematics shown in Figures 2
through 7. Each partitioned schematic is repre-
sented in the system diagram shown in Figure 1.
Notice that the the system diagram also includes
the interconnections between the partitioned
schematics.
CS4330/31/33 Digital to Analog Converter
A description of the CS4330/31/33 is included in
the CS4330/31/33 data sheet.
CS8412 Digital Audio Receiver
The system receives and decodes the standard
S/PDIF data format using a CS8412 Digital
Audio Receiver, Figure 4. The outputs of the
CS8412 include a serial bit clock, serial data,
left-right clock (FSYNC), de-emphasis control
and a 256Fs master clock. The operation of the
CS8412 and a discussion of the digital audio in-
terface are included in the 1994 Crystal
Semiconductor Audio Data Book.
During normal operation, the CS8412 operates in
the Channel Status mode where the LED’s dis-
play channel status information for the channel
selected by the CSLR/FCK jumper. This allows
the CS8412 to decode and supply the de-empha-
sis bit from the digital audio interface for control
of the CS4330/31/33 de-emphasis filter via
pin 3, CC/F0, of the CS8412.
When the Error Information Switch is activated,
the CS8412 operates in the Error and Frequency
information mode. The information displayed by
the LED’s can be decoded by consulting the
CS8412 data sheet. If the Error Information
Switch is activated, and the CS4330/31/33 is in
the internal serial clock mode, then it is likely
that the de-emphasis control for the
CS4330/31/33 will be erroneous and produce an
incorrect audio output.
Encoded sample frequency information can be
displayed provided a proper clock is being ap-
plied to the FCK pin of the CS8412. When an
LED is lit, this indicates a "1" on the corre-
sponding pin located on the CS8412. When an
LED is off, this indicates a "0" on the corre-
sponding pin. Neither the L or R option of
CSLR/FCK should be selected if the FCK pin is
being driven by a clock signal.
The evaluation board has been designed such
that the input can be either optical or coax, Fig-
ure 6. It is not necessary to select the active
input. However, both inputs can not be driven si-
multaneously.
CS8412 Data Format
The CS8412 data format can be set with jumpers
M0, M1, M2, and M3. These formats are shown
in the CS8412 datasheet found in the 1994 Crys-
tal Semiconductor Audio Data Book. The format
selected must be compatible with the corre-
sponding data format of the CS4330/31/33
shown in Figures 4-7 of the CS4330/31/33
datasheet. The default settings for M0-M3 on the
evaluation board are given in Tables 2-4. The
compatible data formats we have chosen for the
CS8412 and CS4330/31/33 are:
CS8412 format 6;CS4330
CS8412 format 2;CS4331 (External SCLK only)
CS8412 format 5;CS4333 (External SCLK only)
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DS136DB2