CS2100-CP Datasheet, PDF (3/32 Pages) Cirrus Logic – Fractional-N Clock Multiplier

CS2100-CP
8.4 Global Configuration (Address 05h) ............................................................................................... 27
8.4.1 Device Configuration Freeze (Freeze) ................................................................................ 27
8.4.2 Enable Device Configuration Registers 2 (EnDevCfg2) ....................................................... 27
8.5 Ratio (Address 06h - 09h) .............................................................................................................. 28
8.6 Function Configuration 1 (Address 16h) ........................................................................................ 28
8.6.1 Clock Skip Enable (ClkSkipEn) ............................................................................................. 28
8.6.2 AUX PLL Lock Output Configuration (AuxLockCfg) .............................................................. 28
8.6.3 Reference Clock Input Divider (RefClkDiv[1:0]) .................................................................... 28
8.7 Function Configuration 2 (Address 17h) ........................................................................................ 29
8.7.1 Enable PLL Clock Output on Unlock (ClkOutUnl) ................................................................. 29
8.7.2 Low-Frequency Ratio Configuration (LFRatioCfg) ................................................................ 29
8.8 Function Configuration 3 (Address 1Eh) ........................................................................................ 29
8.8.1 Clock Input Bandwidth (ClkIn_BW[2:0]) ................................................................................ 29
9. CALCULATING THE USER DEFINED RATIO .................................................................................... 30
9.1 High Resolution 12.20 Format ....................................................................................................... 30
9.2 High Multiplication 20.12 Format ................................................................................................... 30
10. PACKAGE DIMENSIONS .................................................................................................................. 31
THERMAL CHARACTERISTICS ......................................................................................................... 31
11. ORDERING INFORMATION .............................................................................................................. 32
12. REFERENCES .................................................................................................................................... 32
13. REVISION HISTORY .......................................................................................................................... 32
LIST OF FIGURES
Figure 1. Typical Connection Diagram ........................................................................................................ 5
Figure 2. Control Port Timing - I²C Format .................................................................................................. 8
Figure 3. Control Port Timing - SPI Format (Write Only) ............................................................................ 9
Figure 4. Delta-Sigma Fractional-N Frequency Synthesizer ..................................................................... 10
Figure 5. Hybrid Analog-Digital PLL .......................................................................................................... 11
Figure 6. Internal Timing Reference Clock Divider ................................................................................... 12
Figure 7. External Component Requirements for Crystal Circuit .............................................................. 12
Figure 8. CLK_IN removed for > 2²³ SysClk cycles .................................................................................. 14
Figure 9. CLK_IN removed for < 2²³ SysClk cycles but > t_CS ................................................................... 14
Figure 10. CLK_IN removed for < t_CS ....................................................................................................... 14
Figure 11. Low bandwidth and new clock domain .................................................................................... 15
Figure 12. High bandwidth with CLK_IN domain re-use ........................................................................... 15
Figure 13. Ratio Feature Summary ........................................................................................................... 19
Figure 14. PLL Clock Output Options ....................................................................................................... 20
Figure 15. Auxiliary Output Selection ........................................................................................................ 20
Figure 16. Control Port Timing in SPI Mode ............................................................................................. 22
Figure 17. Control Port Timing, I²C Write .................................................................................................. 23
Figure 18. Control Port Timing, I²C Aborted Write + Read ....................................................................... 23
LIST OF TABLES
Table 1. PLL Input Clock Range Indicator ................................................................................................ 13
Table 2. Ratio Modifier .............................................................................................................................. 17
Table 3. Automatic Ratio Modifier ............................................................................................................. 17
Table 4. Example Audio Oversampling Clock Generation from CLK_IN .................................................. 18
Table 5. Example 12.20 R-Values ............................................................................................................ 30
Table 6. Example 20.12 R-Values ............................................................................................................ 30
DS840PP1
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