CS2100-CP Datasheet, PDF (19/32 Pages) Cirrus Logic – Fractional-N Clock Multiplier

5.3.5
CS2100-CP
Ratio Configuration Summary
The R_UD is the user defined ratio stored in the register space. The resolution for the R_UD is selectable by
setting LFRatioCfg. R-Mod is applied if selected. The user defined ratio, ratio modifier, and automatic ratio
modifier make up the effective ratio R_EFF, the final calculation used to determine the output to input clock
ratio. The effective ratio is then corrected for the internal dividers. The conceptual diagram in Figure 13
summarizes the features involved in the calculation of the ratio values used to generate the fractional-N
value which controls the Frequency Synthesizer.
RefClkDiv[1:0]
Timing Reference Clock
(XTI/REF_CLK)
Effective Ratio REFF
Divide
SysClk
Frequency
Synthesizer
PLL Output
User Defined Ratio RUD
Ratio
Ratio Format
12.20
20.12
RModSel[2:0]
Ratio
Modifier
Auto
R-Mod
RefClkDiv[1:0]
R Correction
N
Digital PLL &
Fractional N Logic
LFRatioCfg
AutoRMod
FsDet[1:0]
Frequency Reference Clock
(CLK_IN)
Figure 13. Ratio Feature Summary
Referenced Control
Register Location
Ratio......................................“Ratio (Address 06h - 09h)” on page 28
LFRatioCfg ............................“Low-Frequency Ratio Configuration (LFRatioCfg)” on page 29
RModSel[2:0] ........................“R-Mod Selection (RModSel[2:0])” section on page 26
AutoRMod .............................“Auto R-Modifier Enable (AutoRMod)” on page 26
FsDet[1:0]..............................“PLL Input Sample Rate Indicator (FsDet[1:0]) - Read Only” section on page 25
RefClkDiv[1:0] .......................“Reference Clock Input Divider (RefClkDiv[1:0])” on page 28
DS840PP1
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