CS2000-OTP_09 Datasheet, PDF(23/30 Page) Cirrus Logic – Fractional-N Clock Synthesizer & Clock Multiplier

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CS2000-OTP_09 Datasheet, PDF (23/30 Pages) Cirrus Logic – Fractional-N Clock Synthesizer & Clock Multiplier

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6.1.2

CS2000-OTP

Auxiliary Output Source Selection (AuxOutSrc[1:0])

Selects the source of the AUX_OUT signal.

AuxOutSrc[1:0]

Application:

Auxiliary Output Source

RefClk.

CLK_IN.

CLK_OUT.

PLL Lock Status Indicator.

âAuxiliary Outputâ on page 18

Note: When set to 11, the AuxLockCfg global parameter sets the polarity and driver type (âAUX PLL

Lock Output Configuration (AuxLockCfg)â on page 24).

6.1.3

Lock Clock Ratio (LockClk[1:0])

Selects one of the four stored User Defined Ratios for use in the dynamic ratio based Hybrid PLL Mode.

LockClk[1:0]

Application:

CLK_IN Ratio Selection

Ratio 0.

Ratio 1.

Ratio 2.

Ratio 3.

Section 5.4.2 on page 14

Note: The User Defined Ratio for the static ratio based Frequency Synthesizer mode is the ratio that

corresponds with the currently chosen configuration set as shown in Figure 17 on page 22.

6.1.4

Fractional-N Source for Frequency Synthesizer (FracNSrc)

Selects static or dynamic ratio mode when auto clock switching is disabled.

FracNSrc

Application:

Fractional-N Source Selection

Static Ratio directly from REFF for Frequency Synthesizer Mode

Dynamic Ratio from Digital PLL for Hybrid PLL Mode

âFractional-N Source Selectionâ on page 15

6.2 Ratio 0 - 3

The four 32-bit User Defined Ratios are stored in the CS2000âs one time programmable memory. See âOut-

put to Input Frequency Ratio Configurationâ on page 14 and âCalculating the User Defined Ratioâ on

page 26 for more details.

DS758F1

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