CS2000-OTP_09 Datasheet, PDF (13/30 Pages) Cirrus Logic – Fractional-N Clock Synthesizer & Clock Multiplier

CS2000-OTP
which the Frequency Synthesizer multiplies while maintaining synchronicity with the frequency reference
clock through the Digital PLL. The allowable frequency range for CLK_IN is found in the “AC Electrical Char-
acteristics” on page 7.
5.3.1
Adjusting the Minimum Loop Bandwidth for CLK_IN
The CS2000 allows the minimum loop bandwidth of the Digital PLL to be adjusted between 1 Hz and
128 Hz using the ClkIn_BW[2:0] global parameter. The minimum loop bandwidth of the Digital PLL direct-
ly affects the jitter transfer function; specifically, jitter frequencies below the loop bandwidth corner are
passed from the PLL input directly to the PLL output without attenuation. In some applications it is desir-
able to have a very low minimum loop bandwidth to reject very low jitter frequencies, commonly referred
to as wander. In others it may be preferable to remove only higher frequency jitter, allowing the input wan-
der to pass through the PLL without attenuation.
Typically, applications in which the PLL_OUT signal creates a new clock domain from which all other sys-
tem clocks and associated data are derived will benefit from the maximum jitter and wander rejection of
the lowest PLL bandwidth setting. See Figure 11.
Wander > 1 Hz
CLK_IN
Jitter
PLL
BW = 1 Hz
PLL_OUT
Wander and Jitter > 1 Hz Rejected
MCLK
MCLK
LRCK
or
Subclocks generated
from new clock domain.
LRCK
SCLK
SCLK
SDATA
D0
D1
SDATA
Figure 11. Low bandwidth and new clock domain
D0
D1
Systems in which some clocks and data are derived from the PLL_OUT signal while other clocks and data
are derived from the CLK_IN signal will often require phase alignment of all the clocks and data in the
system. See Figure 12. If there is substantial wander on the CLK_IN signal in these applications, it may
be necessary to increase the minimum loop bandwidth allowing this wander to pass through to the
CLK_OUT signal in order to maintain phase alignment. For these applications, it is advised to experiment
with the loop bandwidth settings and choose the lowest bandwidth setting that does not produce system
timing errors due to wandering between the clocks and data synchronous to the CLK_IN domain and
those synchronous to the PLL_OUT domain.
Wander < 128 Hz
CLK_IN
Jitter
PLL
PLL_OUT
BW = 128 Hz
Jitter > 128 Hz Rejected
Wander < 128 Hz Passed to Output
MCLK
MCLK
LRCK
or
Subclocks and data re-used
from previous clock domain.
LRCK
SCLK
SCLK
SDATA
D0
D1
SDATA
Figure 12. High bandwidth with CLK_IN domain re-use
D0
D1
DS758F1
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