CS2000-OTP_09 Datasheet, PDF (14/30 Pages) Cirrus Logic – Fractional-N Clock Synthesizer & Clock Multiplier

CS2000-OTP
While acquiring lock, the digital loop bandwidth is automatically set to a large value. Once lock is
achieved, the digital loop bandwidth will settle to the minimum value selected by the ClkIn_BW[2:0] pa-
rameter.
Referenced Control
Parameter Definition
ClkIn_BW[2:0] .......................“Clock Input Bandwidth (ClkIn_BW[2:0])” on page 25
5.4 Output to Input Frequency Ratio Configuration
5.4.1
User Defined Ratio (R_UD), Frequency Synthesizer Mode
The User Defined Ratio, R_UD, is a 32-bit un-signed fixed-point number which determines the basis for the
desired input to output clock ratio. Up to four different ratios, Ratio_0-3, can be stored in the CS2000’s one
time programmable memory. Selection between the four ratios is achieved by the M[1:0] mode select
pins. The 32-bit R_UD is represented in a high-resolution 12.20 format where the 12 MSBs represent the
integer binary portion while the remaining 20 LSBs represent the fractional binary portion. The maximum
multiplication factor is approximately 4096 with a resolution of 0.954 PPM in this configuration. See “Cal-
culating the User Defined Ratio” on page 26 for more information.
The status of internal dividers, such as the internal timing reference clock divider, are automatically taken
into account. Therefore R_UD is simply the desired ratio of the output to input clock frequencies.
Referenced Control
Parameter Definition
Ratio 0-3................................“Ratio 0 - 3” on page 23
M[1:0] ....................................“M1 and M0 Mode Pin Functionality” on page 19
5.4.2
User Defined Ratio (R_UD), Hybrid PLL Mode
The same four ratio locations, Ratio_0-3, are used to store the User Defined Ratios for Hybrid PLL Mode.
Selection of the User Defined Ratio for the dynamic ratio based Hybrid PLL Mode is made with the M[1:0]
pins (unless auto fractional N source selection is enabled; see section 5.4.5 on page 15).
In addition to the High-Resolution ratio format, a High-Multiplication format is also available. In the High-
Multiplication format mode, the 32-bit fixed-point number for R_UD is represented in a 20.12 format where
the 20 MSBs represent the integer binary portion while the remaining 12 LSBs represent the fractional
binary portion. In this configuration, the maximum multiplication factor is approximately 1,048,575 with a
resolution of 244 PPM.
The 20.12 format is enabled by the LFRatioCfg global parameter. The 20.12 ratio format is only available
when the device is running in Hybrid PLL Mode. In Auto Fractional-N Source Selection Mode (see section
5.4.5.2 on page 16) when CLK_IN is not present the LFRatioCfg parameter is ignored and the ratio format
is 12.20.
It is recommended that the 12.20 High-Resolution format be utilized whenever the desired ratio is less
than 4096 since the output frequency accuracy of the PLL is directly proportional to the accuracy of the
timing reference clock and the resolution of the R_UD.
Referenced Control
Parameter Definition
LockClk[1:0] ..........................“Lock Clock Ratio (LockClk[1:0])” section on page 23
LFRatioCfg ............................“Low-Frequency Ratio Configuration (LFRatioCfg)” on page 24
FracNSrc ...............................“Fractional-N Source for Frequency Synthesizer (FracNSrc)” section on page 23
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