CS2000-OTP_09 Datasheet, PDF (21/30 Pages) Cirrus Logic – Fractional-N Clock Synthesizer & Clock Multiplier

5.8.2
CS2000-OTP
PLL Unlock Conditions
Certain changes to the clock inputs and mode pins can cause the PLL to lose lock which will affect the
presence of a clock signal on CLK_OUT. The following outlines which conditions cause the PLL to go un-
locked:
• Any change in the state of the M1 and M0 pins will cause the PLL to temporarily lose lock as the new
setting takes affect.
• Changes made to the state of the M2 when the M2Config[2:0] global parameter is set to 011, 100, 101,
or 110 can cause the PLL to temporarily lose lock as the new setting takes affect.
• Any discontinuities on the Timing Reference Clock, REF_CLK.
• Discontinuities on the Frequency Reference Clock, CLK_IN.
• Gradual changes in CLK_IN frequency greater than ±30% from the starting frequency.
• Step changes in CLK_IN frequency.
5.9 Required Power Up Sequencing for Programmed Devices
• Apply power. All input pins, except XTI/REF_CLK, should be held in a static logic hi or lo state until the
‘DC Power Supply’ specification in the “Recommended Operating Conditions” table on page 6 are met.
• Apply input clock(s) if required.
• For CDK programmed devices, toggle the state of the M0, M1, or both pins at least 3 times to initialize
the device. This must be done after the power supply is stable and before normal operation is expected.
Note: This operation is not required for factory programmed devices.
• After the specified PLL lock time on page 7 has passed, the device will output the desired clock as con-
figured by the M0-M2 pins.
DS758F1
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