WM8326 Datasheet, PDF (22/255 Pages) Wolfson Microelectronics plc – Processor Power Management Subsystem

WM8326
7.3 RESET THRESHOLDS
Unless otherwise noted: T_J = -40°C to +125°C; Typical values are at T_J = +25ºC
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
Power On Reset
Power on Reset threshold
VPMIC (LDO12VOUT) voltage
at which device transitions
between NO POWER and
BACKUP states
V_{POR, DE-}
ASSERT
V_{POR, ASSERT}
VPMIC rising
VPMIC falling
Power on Reset hysteresis
Device Reset Control
V_{POR, HYST}
Device Reset threshold
VPMIC (LDO12VOUT) voltage
at which device transitions
between BACKUP and OFF
states
V_{RES, DE-}
ASSERT
V_{RES, ASSERT}
VPMIC rising
VPMIC falling
Device Reset hysteresis
Device Shutdown
V_{RES, HYST}
Shutdown threshold
PVDD voltage at which the
device forces an OFF transition
V_SHUTDOWN
PVDD falling
SYSLO threshold accuracy
V_SYSLO
PVDD falling,
-3
PVDD voltage at which SYSLO
is asserted.
V_SYSLO set by SYSLO_THR
(2.8V to 3.5V)
SYSOK threshold accuracy
V_SYSOK
PVDD rising,
-3
PVDD voltage at which SYSOK
is asserted.
V_SYSOK set by SYSOK_THR
(2.8V to 3.5V)
Note the SYSOK hysteresis
margin (V_{SYSOK, HYST}) is added
to SYSOK_THR.
SYSOK hysteresis
V_{SYSOK, HYST}
TYP
1.18
1.08
100
1.89
1.80
90
2.7
40
Production Data
MAX
UNIT
V
V
mV
V
V
mV
V
+3
%
+3
%
mV
7.4 REFERENCES
Unless otherwise noted: T_J = +25ºC
PARAMETER
Voltage Reference
Current Reference
SYMBOL
V_VREFC
V_IREFR
TEST CONDITIONS
100k to GND
MIN
TYP
MAX
UNIT
0.8
V
0.5
V
w
PD, June 2012, Rev 4.0
22