WM8326 Datasheet, PDF (134/255 Pages) Wolfson Microelectronics plc – Processor Power Management Subsystem

WM8326
V_PVDD
VSYSOK
VSYSLO
VSHUTDOWN
Production Data
time
SYSOK (SYSLO)
time
SHUTDOWN
time
Figure 27 PVDD Monitoring
ADDRESS
R16385
(4001h)
PVDD
Control
BIT
15:14
LABEL
SYSLO_ERR_
ACT
11 SYSLO_STS
6:4 SYSLO_THR
[2:0]
2:0 SYSOK_THR
[2:0]
Table 78 PVDD Monitoring Control
DEFAULT
00
0
010
101
DESCRIPTION
SYSLO Error Action
Selects the action taken when SYSLO is
asserted
00 = Interrupt
01 = WAKE transition
10 = Reserved
11 = OFF transition
SYSLO Status
0 = Normal
1 = PVDD is below SYSLO threshold
SYSLO threshold (falling PVDD)
This is the falling PVDD voltage at which
SYSLO will be asserted
000 = 2.8V
001 = 2.9V
…
111 = 3.5V
SYSOK threshold (rising PVDD)
This is the rising PVDD voltage at which
SYSOK will be asserted
000 = 2.8V
001 = 2.9V
…
111 = 3.5V
Note that the SYSOK hysteresis margin is
added to these threshold levels.
w
PD, June 2012, Rev 4.0
134