CS4360 Datasheet, PDF (21/36 Pages) Cirrus Logic – 24-Bit, 192 kHz 6 Channel D/A Converter

CS4360
VQ
17 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. VQ must be capacitively
coupled to analog ground, as shown in the Typical Connection Diagram. The nominal voltage level is
specified in the Analog Characteristics and Specifications section. VQ presents an appreciable source
impedance and any current drawn from this pin will alter device performance. However, VQ can be used
to bias the analog circuitry assuming there is no AC signal component and the DC current is less than
the maximum specified in the Analog Characteristics and Specifications section.
VA
22 Analog Power (Input) - Positive power supply for the analog section. Refer to the Recommended Oper-
ating Conditions for appropriate voltages.
AOUTA1
AOUTB1
AOUTA2
AOUTB2
AOUTA3
AOUTB3
19 Analog Outputs (Output) - The full scale analog line output level is specified in the Analog Characteris-
20 ^{tics specifications table.}
23
24
26
27
MUTEC1
MUTEC2
MUTEC3
18 Mute Control (Output) - The Mute Control pin goes high during power-up initialization, reset, muting,
25 power-down or if the master clock to left/right clock frequency ratio is incorrect. This pin is intended to be
28 used as a control for an external mute circuit to prevent the clicks and pops that can occur in any single
supply system. The use of an external mute circuit is not mandatory but may be desired for designs
requiring the absolute minimum in extraneous clicks and pops.
Control Port
Definitions
SCL/CCLK
11 Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an external pull-up
resistor to the logic interface voltage in Two-Wire mode as shown in the Typical Connection Diagram.
SDA/CDIN
12 Serial Control Data (Input/Output) - SDA is a data I/O line in Two-Wire format and requires an external
pull-up resistor to the logic interface voltage, as shown in the Typical Connection Diagram. CDIN is the
input data line for the control port interface in SPI format.
AD0/CS
13 Address Bit 0 (Two-Wire) / Control Port Chip Select (SPI) (Input/Output) - AD0 is a chip address pin
Two-Wire format; CS is the chip select signal for SPI format.
Stand-Alone
Definitions
DIF1
DIF0
11 Digital Interface Format (Input) - The required relationship between the Left/Right clock, serial clock
12 ^{and serial data is defined by the Digital Interface Format selection. Refer to Table 4.}
DIF1
0
0
1
1
DIF0
0
1
0
1
DESCRIPTION
Left Justified, up to 24-bit data
I²S, up to 24-bit data
Right Justified, 16-bit data
Right Justified, 24-bit data
Table 4. Digital Interface Formats - Stand Alone Mode
M1
13 Mode Selection (Input) - Determines the operational mode of the device as detailed in Table 5.
M2
15
M2
M1
MODE
0
0
Single-Speed without de-emphasis (4 to 50 kHz sample rates)
0
1
Single-Speed with de-emphasis (32 to 48 kHz sample rates)
1
0
Double-Speed (50 to 100 kHz sample rates)
1
1
Quad-Speed (100 to 200 kHz sample rates)
Table 5. Mode Selection
DS517PP1
21