CS4360 Datasheet, PDF (11/36 Pages) Cirrus Logic – 24-Bit, 192 kHz 6 Channel D/A Converter

CS4360
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
(For -KS & -KZ parts T_A = -10 to +70°C; for -BS & -BZ parts T_A = -40 to +85°C; VLC = 1.7 V - 5.5 V; Inputs: Logic
0 = GND, Logic 1 = VLC, C_L = 30 pF)
Parameter
Symbol
Min
Max
Unit
CCLK Clock Frequency
f_sclk
-
6
MHz
RST Rising Edge to CS Falling
t_srs
500
-
ns
CCLK Edge to CS Falling
(Note 20)
t_spi
500
-
ns
CS High Time Between Transmissions
t_csh
1.0
-
µs
CS Falling to CCLK Edge
t_css
20
-
ns
CCLK Low Time
t_scl
66
-
ns
CCLK High Time
t_sch
66
-
ns
CDIN to CCLK Rising Setup Time
t_dsu
40
-
ns
CCLK Rising to DATA Hold Time
(Note 21)
t_dh
15
-
ns
Rise Time of CCLK and CDIN
(Note 22)
t_r2
-
100
ns
Fall Time of CCLK and CDIN
(Note 22)
t_f2
-
100
ns
Notes: 20. t_spi only needed before first falling edge of CS after RST rising edge. t_spi = 0 at all other times.
21. Data must be held for sufficient time to bridge the transition time of CCLK.
22. For F_SCK < 1 MHz.
RST
t _srs
CS
CCLK
CDIN
t _spi t _css
t _scl t _sch
t _csh
t _r2
t _f2
t _{dsu t dh}
Figure 3. Control Port Timing - SPI Format
DS517PP1
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