CS4360 Datasheet, PDF (10/36 Pages) Cirrus Logic – 24-Bit, 192 kHz 6 Channel D/A Converter

CS4360
SWITCHING CHARACTERISTICS- CONTROL PORT- TWO-WIRE FORMAT
(Note 16) (For -KS & -KZ parts T_A = -10 to +70°C; for -BS & -BZ parts T_A = -40 to +85°C; VLC = 1.7 V - 5.5 V;
Inputs: Logic 0 = GND, Logic 1 = VLC, C_L = 30 pF)
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
f_scl
-
100
kHz
RST Rising Edge to Start
t_irs
500
-
ns
Bus Free Time Between Transmissions
t_buf
4.7
-
µs
Start Condition Hold Time (prior to first clock pulse)
t_hdst
4.0
-
µs
Clock Low time
t_low
4.7
-
µs
Clock High Time
t_high
4.0
-
µs
Setup Time for Repeated Start Condition
t_sust
4.7
-
µs
SDA Hold Time from SCL Falling
(Note 17) t_hdd
0
-
µs
SDA Setup time to SCL Rising
t_sud
250
-
ns
Rise Time of SCL and SDA
t_rc, t_rc
-
1
µs
Fall Time SCL and SDA
t_fc, t_fc
-
300
ns
Setup Time for Stop Condition
t_susp
4.7
-
µs
Acknowledge Delay from SCL Falling
(Note 18)
t_ack
-
(Note 19)
ns
Notes: 16. The Two-Wire Format is compatible with the I²C protocol.
17. Data must be held for sufficient time to bridge the transition time, t_fc, of SCL.
18. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.
19. _{2----5---6---5-×-----F----s} for Single-Speed Mode, _{1----2---8---5-×-----F----s} for Double-Speed Mode, _{6----4----×}^5-----F----s for Quad-Speed Mode.
RST
t _irs
Stop
Start
SDA
t _buf
t _hdst
t _high
R e p e ate d
Start _{t rd}
t _hdst
Stop
t _fd
t _fc
t _susp
SCL
t
low
t
hdd
t _sud t _ack
t _sust
t _rc
Figure 2. Control Port Timing - Two-Wire Format
10
DS517PP1