CS4353 Datasheet, PDF (20/28 Pages) Cirrus Logic – 3.3 V Stereo Audio DAC with 2 VRMS Line Output

4.8 Recommended Power-Up and Power-Down Sequences
CS4353
4.8.1 Power-Up Sequences
4.8.1.1 External RESET Power-Up Sequence
Follow the power-up sequence below if the external RESET pin is used:
1. Hold RESET low while the power supplies are turned on.
2. Set the I²S/LJ, 1_2VRMS, and DEM configuration pins to the desired state.
3. Provide the correct MCLK, LRCK, and SCLK signals locked to the appropriate frequencies as
discussed in Section 4.3.
4. After the power supplies, configuration pins, and clock signals are stable, bring RESET high. The
device will initiate the power-up sequence seen in Figure 9. The sequence will complete and audio
will be output from AOUTx within 50 ms after RESET is set high.
4.8.1.2 Internal Power-On Reset Power-Up Sequence
Follow the power-up sequence below if the internal power-on reset is used:
1. Hold RESET high (connected to VL) while the power supplies are turned on. The power-on reset
circuitry will function as described in Section 4.6.
2. Set the I²S/LJ, 1_2VRMS, and DEM configuration pins to the desired state.
3. After the power supplies and configuration pins are stable, provide the correct MCLK, LRCK, and
SCLK signals to progress from the ‘Power-Down State’ in the power-up sequence seen in Figure 9.
The sequence will complete and audio will be output from the AOUTx pins within 50 ms after valid
clocks are applied.
4.8.2 Power-Down Sequences
4.8.2.1 External RESET Power-Down Sequence
Follow the power-down sequence below if the external RESET pin is used:
1. For minimal pops, set the input digital data to zero for at least 8192 consecutive samples.
2. Bring RESET low.
3. Remove the power supply voltages.
4.8.2.2 Internal Power-On Reset Power-Down Sequence
Follow the power-down sequence below if the internal power-on reset is used:
1. For minimal pops, set the input digital data to zero for at least 8192 consecutive samples.
2. Remove the MCLK signal without applying any glitched pulses to the MCLK pin.
3. Remove the power supply voltages.
Note: A glitched pulse is any pulse that is shorter than the period defined by the minimum/maximum
MCLK signal duty cycle specification and the nominal frequency of the input MCLK signal. A transient may
occur on the analog outputs if the MCLK signal duty cycle specification is violated when the MCLK signal
is removed during normal operation; see “Switching Specifications - Serial Audio Interface” on page 10.
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DS803PP1