CS4353 Datasheet, PDF (10/28 Pages) Cirrus Logic – 3.3 V Stereo Audio DAC with 2 VRMS Line Output

SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE
Parameters
MCLK Frequency
MCLK Duty Cycle
Input Sample Rate (Auto selection)
LRCK Duty Cycle
SCLK Pulse Width Low
SCLK Pulse Width High
SCLK Period
SCLK rising to LRCK edge delay
SCLK rising to LRCK edge setup time
SDIN valid to SCLK rising setup time
SCLK rising to SDIN hold time
Symbol
Single-Speed Mode Fs
Double-Speed Mode Fs
Quad-Speed Mode Fs
Single-Speed Mode
t_sclkl
t_sclkh
Double-Speed Mode
Quad-Speed Mode
t_slrd
t_slrs
t_sdlrs
t_sdh
Min
2.048
45
8
84
170
40
20
20
----------1-----------
( 128 ) F s
(^{---6---4--1--})^--F^----s^--
(^{---6---4--1--})^--F^----s^--
20
20
20
20
CS4353
Max
51.2
55
54
108
216
60
-
-
-
-
-
-
-
-
-
Units
MHz
%
kHz
kHz
kHz
%
ns
ns
s
s
s
ns
ns
ns
ns
LRCK
SCLK
SDATA
t _slrd
t _sdlrs
t _slrs
t _sclkh
t _sclkl
t _sdh
Figure 1. Serial Input Timing
10
DS803PP1