CS4353 Datasheet, PDF (16/28 Pages) Cirrus Logic – 3.3 V Stereo Audio DAC with 2 VRMS Line Output

CS4353
4.4 Digital Interface Format
The device will accept audio samples in either I²S or Left-Justified digital interface formats, as illustrated in
Table 7.
The desired format is selected via the I²S/LJ pin. For an illustration of the required relationship between the
LRCK, SCLK and SDIN, see Figures 5-6. For all formats, SDIN is valid on the rising edge of SCLK. Also,
SCLK must have at least 32 cycles per LRCK period in the Left-Justified format.
For more information about serial audio formats, refer to Cirrus Logic Application Note AN282: The 2-Chan-
nel Serial Audio Interface: A Tutorial, available at http://www.cirrus.com.
I²S/LJ
Description
0 I²S, up to 24-bit Data
1 Left-Justified, up to 24-bit Data
Table 7. Digital Interface Format
Figure
5
6
LRCK
SCLK
SDIN
Left Channel
Right Channel
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Figure 5. I²S, up to 24-Bit Data
LRCK
SCLK
SDIN
Left Channel
Right Channel
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Figure 6. Left-Justified up to 24-Bit Data
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DS803PP1