CS4353 Datasheet, PDF (15/28 Pages) Cirrus Logic – 3.3 V Stereo Audio DAC with 2 VRMS Line Output

CS4353
4.2 Sample Rate Range/Operational Mode Detect
The CS4353 operates in one of three operational modes. The device will auto-detect the correct mode when
the input sample rate (Fs), defined by the LRCK frequency, falls within one of the ranges illustrated in
Table 3. Sample rates outside the specified range for each mode are not supported. In addition to a valid
LRCK frequency, a valid serial clock (SCLK) and master clock (MCLK) must also be applied to the device
for speed mode auto-detection; see Figure 9.
Input Sample Rate (Fs)
8 kHz - 54 kHz
84 kHz - 108 kHz
170 kHz - 216 kHz
Mode
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Table 3. CS4353 Operational Mode Auto-Detect
4.3 System Clocking
The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK) clocks.
The left/right clock, defined also as the input sample rate (Fs), must be synchronously derived from the
MCLK signal according to specified ratios. The specified ratios of MCLK to LRCK, along with several stan-
dard audio sample rates and the required MCLK frequency, are illustrated in Tables 4-6.
Refer to Section 4.4 for the required SCLK timing associated with the selected Digital Interface Format and
to “Switching Specifications - Serial Audio Interface” on page 10 for the maximum allowed clock frequen-
cies.
Sample Rate
(kHz)
32
44.1
48
256x
8.1920
11.2896
12.2880
384x
12.2880
16.9344
18.4320
MCLK (MHz)
512x
16.3840
22.5792
24.5760
768x
24.5760
33.8688
36.8640
Table 4. Single-Speed Mode Standard Frequencies
Sample Rate
(kHz)
88.2
96
128x
11.2896
12.2880
192x
16.9344
18.4320
MCLK (MHz)
256x
22.5792
24.5760
384x
33.8688
36.8640
Table 5. Double-Speed Mode Standard Frequencies
Sample Rate
(kHz)
176.4
192
128x
22.5792
24.5760
MCLK (MHz)
192x
33.8688
36.8640
256x
45.1584
49.1520
Table 6. Quad-Speed Mode Standard Frequencies
1024x
32.7680
45.1584
49.1520
512x
45.1584
49.1520
DS803PP1
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