CS2200-OTP Datasheet, PDF (18/22 Pages) Cirrus Logic – Fractional-N Frequency Synthesizer

6.3.3
CS2200-OTP
Enable PLL Clock Output on Unlock (ClkOutUnl)
Defines the state of the PLL output during the PLL unlock condition.
ClkOutUnl
0
1
Application:
Clock Output Enable Status
Clock outputs are driven ‘low’ when PLL is unlocked.
Clock outputs are always enabled (results in unpredictable output when PLL is unlocked).
“PLL Clock Output” on page 12
6.3.4
M2 Pin Configuration (M2Config[2:0])
Controls which special function is mapped to the M2 pin.
M2Config[2:0]
000
001
010
011
100
101
110
111
Application:
M2 pin function
Disable CLK_OUT pin.
Disable AUX_OUT pin.
Disable CLK_OUT and AUX_OUT.
RModSel[1:0] Modal Parameter Enable.
Reserved.
Reserved.
Reserved.
Force AuxOutSrc[1:0] = 10 (PLL Clock Out).
“M2 Mode Pin Functionality” on page 14
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DS842PP1