CS2200-OTP Datasheet, PDF (12/22 Pages) Cirrus Logic – Fractional-N Frequency Synthesizer

CS2200-OTP
tures involved in the calculation of the ratio values used to generate the fractional-N value which controls
the Frequency Synthesizer. The subscript ‘4’ indicates the modal parameters.
Timing Reference Clock
(XTI/REF_CLK)
Divide
RefClkDiv[1:0]
Effective Ratio REFF
M[1:0] pins
User Defined Ratio RUD
Ratio 0
Ratio 1
Ratio 2
Ratio Format
12.20
Ratio 3
M2 pin
RModSel[1:0]4
RefClkDiv[1:0]
Ratio
Modifier
R Correction
SysClk
Static Ratio, ‘N’
Frequency
Synthesizer
PLL Output
Figure 5. Ratio Feature Summary
Referenced Control
Parameter Definition
Ratio 0-3................................“Ratio 0 - 3” on page 17
M[1:0] pins.............................“M1 and M0 Mode Pin Functionality” on page 13
RModSel[1:0] ........................“R-Mod Selection (RModSel[1:0])” section on page 16
RefClkDiv[1:0] .......................“Reference Clock Input Divider (RefClkDiv[1:0])” on page 17
5.4 PLL Clock Output
The PLL clock output pin (CLK_OUT) provides a buffered version of the output of the frequency synthesizer.
The driver can be set to high-impedance with the M2 pin when the M2Config[1:0] global parameter is set to
either 000 or 010. The output from the PLL automatically drives a static low condition while the PLL is un-
locked (when the clock may be unreliable). This feature can be disabled by setting the ClkOutUnl global
parameter, however the state CLK_OUT may then be unreliable during an unlock condition.
ClkOutUnl
PLL Locked/Unlocked
0
0
2:1 Mux
1
0
2:1 Mux
M2 pin with
M2Config[1:0] = 000, 010
PLL Clock Output
PLLClkOut
PLL Clock Output Pin
(CLK_OUT)
PLL Output
1
Figure 6. PLL Clock Output Options
Referenced Control
Parameter Definition
ClkOutUnl..............................“Enable PLL Clock Output on Unlock (ClkOutUnl)” on page 18
ClkOutDis ..............................“M2 Configured as Output Disable” on page 14
M2Config[2:0]........................“M2 Pin Configuration (M2Config[2:0])” on page 18
12
DS842PP1