CS4349 Datasheet, PDF (14/40 Pages) Cirrus Logic – 192 kHz DAC w/ Volume Control and 1 Vrms @ 3.3 V

.
LRCK
(input)
SCLK
(input)
SDIN
(input)
t_lckd
t_lcks
t_sckh
t_sckl
t_ds
t_dh
MSB
MSB-1
Figure 6. Serial Port Timing, Non-TDM Mode
CS4349
LRCK
(Input)
tfss
tlrckh
tfsh
tsckh
tsckl
SCLK
(Input)
SDIN
(Input)
tds
tdh
MSB
MSB-1
Figure 7. Serial Port Timing, TDM Mode
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT
Inputs: Logic 0 = GND; Logic 1 = VLC; C_L = 20 pF.
Parameter
SCL Clock Frequency
RST Rising Edge to Start
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 9)
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
Fall Time SCL and SDA
Setup Time for Stop Condition
Acknowledge Delay from SCL Falling
Symbol
f_scl
t_irs
t_buf
t_hdst
t_low
t_high
t_sust
t_hdd
t_sud
t_rc, t_rc
t_fc, t_fc
t_susp
t_ack
Min
-
500
4.7
4.0
4.7
4.0
4.7
0
250
-
-
4.7
300
Max
100
-
-
-
-
-
-
-
-
1
300
-
1000
Note: 9. Data must be held for sufficient time to bridge the transition time, t_fc, of SCL.
Unit
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
RST
t _irs
Stop
Start
SDA
t _buf
t _hdst
t _high
Repeated
Sta rt _{t rd}
t _hdst
Stop
t _fd
t _fc
t _susp
SCL
t
low
t
hdd
t _sud t _ack
t _sust
t _rc
Figure 8. Control Port Timing - I²C Format
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DS782F1