CAT25C64_06 Datasheet, PDF (9/16 Pages) Catalyst Semiconductor – 64K-Bit SPI Serial CMOS EEPROM

CAT25C64
state and receive an instruction. After a successful byte/
page write or status register write the CAT25C64 goes into
a write disable mode. CS must be set high after the proper
number of clock cycles to start an internal write cycle.
Access to the array during an internal write cycle is
ignored and program-ming is continued. On power up,
Figure 8. Page Write Instruction Timing
CS
SO is in a high impedance.
When powering down, the supply should be taken down
to 0V, so that the CAT25C64 will be reset when power
is ramped back up. If this is not possible, then, following
a brown-out episode, the CAT25C64 can be reset by
refreshing the contents of the Status Register (See
Application Note AN10).
SCK
SI
012345678
21 22 23 24-31 32-39 ^{24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1}
OPCODE
00 00 00
10
ADDRESS
DATA IN
Data Data Data
Byte 1 Byte 2 Byte 3
Data Byte N
7..1
0
SO
Note: Dashed Line = mode (1, 1) – – – –
HIGH IMPEDANCE
Figure 9. HOLD Timing
CS
SCK
HOLD
tCD
tHD
tCD
tHD
tHZ
SO
Note: Dashed Line= mode (1, 1) — — — —
HIGH IMPEDANCE
tLZ
Figure 10. WP Timing
CS
SCK
WP
WP
Note: Dashed Line= mode (1, 1) — — — —
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
t_WPS
t_WPH
t_CSH
9
Doc. No. 1112, Rev. B