CAT25C64_06 Datasheet, PDF (4/16 Pages) Catalyst Semiconductor – 64K-Bit SPI Serial CMOS EEPROM

CAT25C64
FUNCTIONAL DESCRIPTION
The CAT25C64 supports the SPI bus data transmission
protocol. The synchronous Serial Peripheral Interface
(SPI) helps the CAT25C64 to interface directly with
many of today’s popular microcontrollers. The CAT25C64
contains an 8-bit instruction register. (The instruction
set and the operation codes are detailed in the instruction
set table)
After the device is selected with CS going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
The first byte contains one of the six op-codes that define
the operation to be performed.
PIN DESCRIPTION
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
25C64. Input data is latched on the rising edge of the
serial clock.
SO: Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the 25C64. During a read cycle, data
is shifted out on the falling edge of the serial clock.
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to synchronize
Figure 1. Sychronous Data Timing
V_IH
CS
V_IL
V_IH
SCK
V_IL
V_IH
SI
VIL
t_CSS
t_WH
t_SU
t_H
VALID IN
V_OH
SO
V_OL
HI-Z
Note: Dashed Line= mode (1, 1) — — — —
t_CS
t_CSH
t_WL
t_RI
tFI
t_V
t_HO
t_DIS
HI-Z
INSTRUCTION SET
Instruction
WREN
WRDI
RDSR
WRSR
READ
WRITE
Opcode
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Operation
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
Doc. No. 1112, Rev. B
4
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice