CAT25C33_05 Datasheet, PDF (9/11 Pages) Catalyst Semiconductor – 32K/64K-Bit SPI Serial CMOS EEPROM

CAT25C33/65
DESIGN CONSIDERATIONS
The CAT25C33/65 powers up in a write disable state When powering down, the supply should be taken down
and in a low power standby mode. A WREN instruction to 0V, so that the CAT25C33/65 will be reset when power
must be issued to perform any writes to the device after is ramped back up. If this is not possible, then, following
power up. Also,on power up CS should be brought low a brown-out episode, the CAT25C33/65 can be reset by
to enter a ready state and receive an instruction. After refreshing the contents of the Status Register (See Appli-
a successful byte/page write or status register write the cation Note AN10).
CAT25C33/65 goes into a write disable mode. CS must
be set high after the proper number of clock cycles to
start an internal write cycle. Access to the array during
an internal write cycle is ignored and program-ming
is continued. On power up, SO is in a high impedance.
ts _{Figure 8. Page Write Instruction Timing}
r _CS
a _{0 1 2 3 4 5 6 7 8}
21 22 23 24-31 32-39 ^{24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1}
P _SK
OPCODE
d _SI
00 00 00 10
ADDRESS
DATA IN
Data Data Data
Byte 1 Byte 2 Byte 3
Data Byte N
7..1
0
e _{HIGH IMPEDANCE}
SO
u _{Note: Dashed Line = mode (1, 1) – – – –}
tin _{Figure 9. HOLD Timing}
n _CS
co _SCK
Dis ^HOLD
tCD
tHD
tHZ
tCD
tHD
HIGH IMPEDANCE
SO
tLZ
Note: Dashed Line= mode (1, 1) — — — —
© 2005 by Catalyst Semiconductor, Inc.
9
Characteristics subject to change without notice
Doc No. 1000, Rev. H