CAT25C33_05 Datasheet, PDF (8/11 Pages) Catalyst Semiconductor – 32K/64K-Bit SPI Serial CMOS EEPROM

CAT25C33/65
If the write operation is initiated immediately after the The Status Register can be read to determine if the write cycle
WREN instruction without CS being brought high, is still in progress. If Bit 0 of the Status Register is set at 1, write
the data will not be written to the array because the cycle is in progress. If Bit 0 is set at 0, the device is ready for
write enable latch will not have been properly set. the next instruction.
Also, for a successful write operation the address of
the memory location(s) to be programmed must be
outside the protected address field location selected
by the block protection level.
Page Write
The CAT25C33/65 features page write capability. After the first
initial byte the host may continue to write up to 64 bytes of data
to the CAT25C33/65. After each byte of data is received, six
Byte Write
lower order address bits are internally incremented by one; the
Once the device is in a Write Enable state, the user ^{high order bits of address will remain constant. The only}
may proceed with a write sequence by setting the CS ^{restriction is that the 64 bytes must reside on the same page.}
low, issuing a write instruction via the SI line, followed ^{If the address counter reaches the end of the page and clock}
by the 16-bit address (the three Most Significant Bits ^{continues, the counter will “roll over” to the first address of the}
ts ^{are don’t care for 25C65 and four most significant bits page and overwrite any data that may have been written. The}
are don't care for 25C33), and then the data to be ^{CAT25C33/65 is automatically returned to the write disable}
r ^{written. Programming will start after the CS is state at the completion of the write cycle. Figure 8 illustrates the}
brought high. Figure 6 illustrates byte write se- ^{page write sequence.}
a ^quence.
To write to the status register, the WRSR instruction should be
During an internal write cycle, all commands will be ^{sent. Only Bit 2, Bit 3 and Bit 7 of the status register can be}
P ^{ignored except the RDSR (Read Status Register) written using the WRSR instruction. Figure 7 illustrates the}
instruction.
sequence of writing to status register.
d _{Figure 6. Write Instruction Timing}
e _CS
u 0 1 2 3 4 5 6 7 8
21 22 23 24 25 26 27 28 29 30 31
SK
tin ^OPCODE
SI
00 00 00 10
ADDRESS
DATA IN
D7 D6 D5 D4 D3 D2 D1 D0
n _SO
HIGH IMPEDANCE
o _{Note: Dashed Line= mode (1, 1) – – – –}
c _{Figure 7. WRSR Instruction Timing}
is ^CS
D⁰
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCK
OPCODE
DATA IN
SI
0
0
0
0
0
0
0
1
7
6
5
4
3
2
10
MSB
SO
HIGH IMPEDANCE
Note: Dashed Line= mode (1, 1) — — — —
Doc. No. 1000, Rev. H
8
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice